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368 条记录 (耗时 0.043 秒)

    Circuit cell based semiconductor integrated circuit device and method of arrangement-interconnection therefor
    91.
    发明授权
    Circuit cell based semiconductor integrated circuit device and method of arrangement-interconnection therefor 有权
    基于电路单元的半导体集成电路器件及其布置互连方法

    公开(公告)号：US6100550A

    公开(公告)日：2000-08-08

    申请号：US241079

    申请日：1999-02-01

    申请人： Hideto Hidaka

    发明人： Hideto Hidaka

    IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10

    CPC分类号： H01L27/0207 ,  H01L27/118

    摘要： In a circuit cell band having circuit cells arranged aligned along a linear array, an on-a-cell line is arranged over a prescribed number of circuit cells, in a region different from a line region in which line band is formed on both sides of the circuit cells, for example, and the on-the-cell line is connected to a feed through in a feed through region provided between adjacent circuit cells. Restrictions on the feed through, size of the circuit cell and the lines are removed as much as possible. The circuit cell has also island-shaped impurity regions for fixing a substrate potential, so that latch up immunity is improved. Transistor forming regions having different conductivity types in a circuit cell are arranged in a sandwiched structure, and the circuit cell can be inverted horizontally and/or vertically while maintaining the transistor arrangement in the circuit cell. Therefore, position of the signal input/output port of the circuit cell can be changed in accordance with the layout of external lines, whereby optimization of the external line layout is facilitated.

    摘要翻译： 在具有沿着线性阵列排列的电路单元的电路单元频带中，在与规定数量的电路单元相对的区域上布置有单元线，该区域与形成有线带的区域不同 电路单元和例如电池单元线路连接到在相邻电路单元之间提供的馈通区域中的馈电线路。 通过尽可能多地去除馈电通道，电路单元的大小和线路的限制。 电路单元还具有用于固定衬底电位的岛状杂质区域，从而提高了闭锁抗扰度。 在电路单元中具有不同导电类型的晶体管形成区域被布置成夹层结构，并且可以在将晶体管布置保持在电路单元中的同时水平和/或垂直地反转电路单元。 因此，可以根据外部线路的布局来改变电路单元的信号输入/输出端口的位置，从而便于外部线路布局的优化。

    Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions
    93.
    发明授权
    Semiconductor memory device including memory cell transistors formed on SOI substrate and having fixed body regions 失效

    公开(公告)号：US6018172A

    公开(公告)日：2000-01-25

    申请号：US501525

    申请日：1995-07-12

    申请人： Hideto Hidaka ,  Takahiro Tsuruda ,  Katsuhiro Suma

    发明人： Hideto Hidaka ,  Takahiro Tsuruda ,  Katsuhiro Suma

    IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L27/10882 ,  H01L27/10897 ,  H01L27/1203 ,  H01L27/10808

    摘要： A semiconductor memory device includes an SOI substrate, a plurality of word lines, a plurality of bit line pairs, a plurality of memory cells and a plurality of body fixing lines. The plurality of word lines are disposed in the row direction on the SOI substrate. The plurality of bit line pairs are disposed in the column direction on the SOI substrate. The plurality of memory cells are located on the SOI substrate and each are disposed correspondingly to one of crossings between the plurality of word lines and the plurality of bit line pairs. Each of the plurality of memory cells includes a capacitor and a transistor. The transistor is connected between the capacitor and one bit line in the corresponding bit line pair. The transistor is turned on in response to the potential of the corresponding word line. The plurality of body fixing lines are disposed on the SOI substrate. The plurality of body fixing lines are supplied with a predetermined potential. The transistors in the plurality of memory cells have source regions, drain regions and body regions located between the source and drain regions. The body regions of the transistors in the plurality of memory cells are connected to the plurality of body fixing lines.

    Data output circuit with reduced output noise
    95.
    发明授权
    Data output circuit with reduced output noise 失效

    公开(公告)号：US5933048A

    公开(公告)日：1999-08-03

    申请号：US891212

    申请日：1997-07-10

    申请人： Hideto Hidaka ,  Masakazu Hirose

    发明人： Hideto Hidaka ,  Masakazu Hirose

    IPC分类号： H03K19/003 ,  H03K17/16

    CPC分类号： H03K19/00361

    摘要： A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

    Input protection circuit for semiconductor device
    97.
    发明授权
    Input protection circuit for semiconductor device 失效
    半导体器件输入保护电路

    公开(公告)号：US5847430A

    公开(公告)日：1998-12-08

    申请号：US865264

    申请日：1997-05-29

    申请人： Hideto Hidaka

    发明人： Hideto Hidaka

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L23/62

    CPC分类号： H01L27/0248 ,  H01L2924/0002

    摘要： Between an external power supply line and an internal power supply line in which an internal power supply potential is transmitted on a substrate region, a high voltage conducting mechanism is provided, which is rendered conductive when a transitional high voltage surge is generated at the external power supply line by electrically connecting the external power supply line and the internal power supply line. Even when the ground line and external power supply line are not arranged parallel to each other, a high voltage conducting mechanism constituted by a field transistor or an insulated gate type field effect transistor having wide width over a long distance can be formed.

    摘要翻译： 在外部电源线和在基板区域上传输内部电源电位的内部电源线之间设置有高压导通机构，当外部电力产生过渡高压浪涌时， 电源线通过电连接外部电源线和内部电源线。 即使地线和外部电源线彼此不平行配置，也可以形成由长距离宽的宽场的场效应晶体管或绝缘栅型场效应晶体管构成的高电压导通机构。

    Potential detecting circuit and semiconductor integrated circuit
    98.
    发明授权
    Potential detecting circuit and semiconductor integrated circuit 失效

    公开(公告)号：US5760614A

    公开(公告)日：1998-06-02

    申请号：US667178

    申请日：1996-06-20

    申请人： Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

    发明人： Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

    IPC分类号： G01R31/28 ,  G01R19/165 ,  G01R31/3185 ,  G05F1/10 ,  H03K5/08 ,  H03K5/153

    CPC分类号： H03K5/08

    摘要： A constant current source (1) is provided between a power supply (VCC) and an intermediate node (N1) and supplies a reference current (IR) which is a constant current between the power supply (VCC) and the intermediate node (N1). A variable resistor (2) is provided between the intermediate node (N1) and a comparison potential (VL) and its resistance value can be set to a desired value. A current flowing in the variable resistor (2) is a comparison current (IC). An amplifier (3) has an input connected to the intermediate node (N1) and amplifies a potential from the intermediate node (N1) to output a level detection signal (GE). Having this configuration, a potential detecting circuit which ensures a stable and controllable detection level is provided.

    Semiconductor memory device having hierarchical boosted power-line scheme
    99.
    发明授权
    Semiconductor memory device having hierarchical boosted power-line scheme 失效
    具有分层升压电力线方案的半导体存储器件

    公开(公告)号：US5652730A

    公开(公告)日：1997-07-29

    申请号：US648607

    申请日：1996-05-15

    申请人： Takashi Kono ,  Kiyohiro Furutani ,  Mikio Asakura ,  Hideto Hidaka

    发明人： Takashi Kono ,  Kiyohiro Furutani ,  Mikio Asakura ,  Hideto Hidaka

    IPC分类号： G11C11/407 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C8/12

    摘要： A DRAM includes an internal boosting circuit, a global power-line, a plurality of blocks, a row decoder, and a POR generating circuit. Each block includes word lines, local power-lines, AND gates, drive transistors, and word line drivers. The AND gate turns a corresponding drive transistor on/off in response to a power on reset signal /POR and a corresponding block select signal. Therefore, all the local boosted power-lines are connected to the global boosted power-line during a power on reset period, whereby all the local boosted power-lines are initially charged up to boosted power supply potential Vpp.

    摘要翻译： DRAM包括内部升压电路，全局电源线，多个块，行解码器和POR发生电路。 每个块包括字线，本地电源线，与门，驱动晶体管和字线驱动器。 AND门响应于上电复位信号/ POR和相应的块选择信号而使相应的驱动晶体管导通/截止。 因此，所有本地升压电源线​​在上电复位期间连接到全局升压电源线​​，由此所有本地升压电源线​​最初都被充电至提升电源电位Vpp。