公开(公告)号：US5898316A

公开(公告)日：1999-04-27

申请号：US673244

申请日：1996-06-27

申请人： Tetsuo Kato ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tetsuo Kato ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/406 ,  G11C11/401 ,  G11C11/407 ,  H03K19/173

CPC分类号： G11C7/1045 ,  G11C11/40611 ,  G11C2211/4061

摘要： Two NAND gates are provided corresponding to each of a plurality of pads. By connecting a mode switching pad to power supply potential or ground potential, one of the two NAND gates provided corresponding to each pad is activated, and the other NAND gate is non-activated. As a result, different mode select signals are provided from the output of each NAND gate.

摘要翻译： 对应于多个焊盘中的每一个提供两个NAND门。 通过将模式切换焊盘连接到电源电位或接地电位，与每个焊盘对应的两个NAND门中的一个被激活，而另一个NAND门不被激活。 结果，从每个NAND门的输出提供不同的模式选择信号。

公开(公告)号：US06469327B1

公开(公告)日：2002-10-22

申请号：US08900515

申请日：1997-07-25

申请人： Kenichi Yasuda ,  Hideto Hidaka ,  Mikio Asakura ,  Tsukasa Ooishi ,  Kei Hamade

发明人： Kenichi Yasuda ,  Hideto Hidaka ,  Mikio Asakura ,  Tsukasa Ooishi ,  Kei Hamade

IPC分类号： H01L2710

CPC分类号： H01L23/50 ,  H01L24/06 ,  H01L24/48 ,  H01L27/0207 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

摘要： Pads are alignedly arranged in a central region of a semiconductor chip and are also arranged at an outer peripheral portion of the central portion of the chip. A pad at the outer peripheral portion is electrically connected to a die pad mounting the chip thereon with an insulative material interposed therebetween. A potential supplied to the pad positioned at the outer peripheral portion can be stabilized by parasitic capacitance of the die pad, and a potential of the die pad can be externally monitored easily by removing away a portion of mold resin after resin sealing. Further, due to a cress shaped arrangement of the pads, a voltage down converter can be arranged in line with the pads and at outer periphery of the chip without area penalty. In testing operation, a switching circuit switches a function of a pad to another pad so that cross-shapedly arranged pads are equivalently arranged in a line.

摘要翻译： 垫片排列在半导体芯片的中心区域中，并且还布置在芯片的中心部分的外周部分。 外周部分的焊盘与安装芯片的芯片焊盘电连接，绝缘材料插入其间。 通过芯片焊盘的寄生电容可以使供给位于外周部的焊盘的电位稳定，并且能够通过在树脂密封后除去一部分模制树脂来容易地外部监视焊盘的电位。 此外，由于焊盘的水平排列，可以将电压降压转换器布置成与焊盘和芯片的外周边一致，而不会造成区域损失。 在测试操作中，切换电路将焊盘的功能切换到另一焊盘，使得十字形布置的焊盘等价地布置成一行。

公开(公告)号：US5953261A

公开(公告)日：1999-09-14

申请号：US76887

申请日：1998-05-13

申请人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

发明人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/38 ,  G11C7/00

CPC分类号： G11C29/38 ,  G11C29/34 ,  G11C7/1051 ,  G11C7/1078

摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

摘要翻译： 与同时选择的多个存储单元相对应地提供的读驱动器被配线或连接到内部读数据总线，内部读数据总线又分别对应于多个存储单元阵列提供。 为内部读取数据总线提供测试模式电路，用于检测这些内部读取数据总线上信号电位逻辑的一致/不一致。 在测试操作中，所有读取驱动器都被激活以读取相应的内部读取数据总线上的选定存储单元数据。

公开(公告)号：US5760614A

公开(公告)日：1998-06-02

申请号：US667178

申请日：1996-06-20

申请人： Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G01R31/28 ,  G01R19/165 ,  G01R31/3185 ,  G05F1/10 ,  H03K5/08 ,  H03K5/153

CPC分类号： H03K5/08

摘要： A constant current source (1) is provided between a power supply (VCC) and an intermediate node (N1) and supplies a reference current (IR) which is a constant current between the power supply (VCC) and the intermediate node (N1). A variable resistor (2) is provided between the intermediate node (N1) and a comparison potential (VL) and its resistance value can be set to a desired value. A current flowing in the variable resistor (2) is a comparison current (IC). An amplifier (3) has an input connected to the intermediate node (N1) and amplifies a potential from the intermediate node (N1) to output a level detection signal (GE). Having this configuration, a potential detecting circuit which ensures a stable and controllable detection level is provided.

公开(公告)号：US06414883B2

公开(公告)日：2002-07-02

申请号：US09860795

申请日：2001-05-21

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US06197643B1

公开(公告)日：2001-03-06

申请号：US09338574

申请日：1999-06-23

申请人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

发明人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： H01L218234

CPC分类号： G11C7/1078 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147

摘要： The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

摘要翻译： 电平转换电路包括第一电流切断电路，第二电流切断电路，电平移位电路和反相器。 第一电流切割电路包括连接到具有升压电位Vpp的节点的两个PMOS晶体管。 第二电流切断电路包括连接到接地节点的两个NMOS晶体管。 电平移位电路包括两个PMOS晶体管和两个NMOS晶体管。 在直流电流在具有升压电位Vpp的节点和接地节点之间流动之前，包括在第一电流切割电路中的任何晶体管和包括在第二电流切割电路中的任何晶体管都被截止。 因此，可以防止具有升压电位Vbb的节点与接地节点之间的电流。

公开(公告)号：US6054885A

公开(公告)日：2000-04-25

申请号：US123462

申请日：1998-07-28

申请人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/403 ,  G06F1/04 ,  G06F1/08 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

CPC分类号： G11C29/028 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401

摘要： A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.

摘要翻译： 测试器连接到设置在DRAM芯片中的信号输出端子，并且监视从内部定时器输出的时钟信号的频率。 通过改变3位信号的组合来改变时钟信号的频率，以获得最接近设定值的频率的信号。 内部定时器中的保险丝断开以设置时钟信号的频率，以获得与施加该信号的情况相同的状态。

公开(公告)号：USRE36089E

公开(公告)日：1999-02-09

申请号：US652008

申请日：1996-05-23

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US06859403B2

公开(公告)日：2005-02-22

申请号：US10815798

申请日：2004-04-02

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

摘要翻译： 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

公开(公告)号：US06272055B1

公开(公告)日：2001-08-07

申请号：US09168962

申请日：1998-10-09

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.