公开(公告)号：US20130237048A1

公开(公告)日：2013-09-12

申请号：US13602404

申请日：2012-09-04

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L21/28

CPC分类号： H01L21/28 ,  H01L27/11558 ,  H01L27/1156 ,  H01L29/401

摘要： The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region.

公开(公告)号：US20130176793A1

公开(公告)日：2013-07-11

申请号：US13344621

申请日：2012-01-06

申请人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ming Ku ,  Yung-Hsiang Chen ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/12

摘要： A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.

摘要翻译： 提供一种闪存装置。 闪存装置包括多个存储单元和多个编程电压控制发生器。 每个存储单元通过其控制端接收编程控制电压，并根据编程控制电压执行数据编程操作。 每个编程电压控制发生器包括预充电电压发射器和泵浦电容器。 预充电电压发射器在第一时段期间根据预充电使能信号向每个相应存储器单元的末端提供预充电电压。 在第二时段期间向泵浦电容器提供泵浦电压，并且在每个存储器单元的控制端产生编程控制电压。

公开(公告)号：US20130010518A1

公开(公告)日：2013-01-10

申请号：US13413626

申请日：2012-03-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00 ,  H01L27/088

CPC分类号： H01L27/11206 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.

摘要翻译： 提供具有耦合通道的反熔丝存储器。 反熔丝存储器包括第一导电类型的衬底，第二导电类型的掺杂区域，耦合栅极，栅极介电层，反熔丝栅极和反熔丝层。 衬底具有隔离结构。 掺杂区域设置在衬底中。 在掺杂区域和隔离结构之间限定沟道区域。 耦合栅极设置在掺杂区域和隔离结构之间的衬底上。 耦合栅极与掺杂区域相邻。 栅极电介质层设置在耦合栅极和衬底之间。 反熔丝栅极设置在耦合栅极和隔离结构之间的衬底上。 反熔丝栅极和耦合栅极之间具有间隔。 反熔丝层设置在反熔丝栅极和衬底之间。

公开(公告)号：US20120223381A1

公开(公告)日：2012-09-06

申请号：US13191424

申请日：2011-07-26

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833

摘要： A non-volatile memory structure is disclosed. LDD regions may be optionally formed through an ion implantation using a mask for protection of a gate channel region of an active area. Two gates are apart from each other and disposed on an isolation structure on two sides of a middle region of the active area, respectively. The two gates may be each entirely disposed on the isolation structure or partially to overlap a side portion of the middle region of the active area. A charge-trapping layer and a dielectric layer are formed between the two gates and on the active area to serve for a storage node function. They may be further formed onto all sidewalls of the two gates to serve as spacers. Source/drain regions are formed through ion implantation using a mask for protection of the gates and the charge-trapping layer.

摘要翻译： 公开了一种非易失性存储器结构。 可以通过使用用于保护有源区的栅极沟道区的掩模的离子注入任选地形成LDD区。 两个门彼此分开并且分别设置在有源区域的中间区域的两侧上的隔离结构上。 两个门可以各自完全设置在隔离结构上，或者部分地与有效区域的中间区域的侧部重叠。 在两个门之间和有源区域上形成电荷俘获层和电介质层，用于存储节点功能。 它们可以进一步形成在两个门的所有侧壁上，用作间隔物。 通过使用用于保护栅极和电荷俘获层的掩模的离子注入形成源/漏区。

公开(公告)号：US20120163072A1

公开(公告)日：2012-06-28

申请号：US13414734

申请日：2012-03-08

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L21/28282 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory cell with dual functions includes a substrate, a first gate, a second gate, a third gate, a charge storage layer, a first diffusion region, a second diffusion region, and a third diffusion region. The second gate and the third gate are used for receiving a first voltage corresponding to a one-time programming function of the dual function and a second voltage corresponding to a multi-time programming function of the dual function. The first diffusion region is used for receiving a third voltage corresponding to the one-time programming function and a fourth voltage corresponding to the multi-time programming function. The second diffusion region is used for receiving a fifth voltage corresponding to the multi-time programming function.

摘要翻译： 具有双重功能的非易失性半导体存储单元包括基板，第一栅极，第二栅极，第三栅极，电荷存储层，第一扩散区域，第二扩散区域和第三扩散区域。 第二栅极和第三栅极用于接收对应于双功能的一次编程功能的第一电压和对应于双功能的多次编程功能的第二电压。 第一扩散区用于接收对应于一次编程功能的第三电压和对应于多次编程功能的第四电压。 第二扩散区用于接收对应于多次编程功能的第五电压。

公开(公告)号：US07960792B2

公开(公告)日：2011-06-14

申请号：US12943945

申请日：2010-11-11

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L29/786 ,  H01L29/792

CPC分类号： H01L27/115

摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.

摘要翻译： 设置在SOI衬底中的非易失性存储器。 非易失性存储器包括存储单元和第一导电类型掺杂区域。 存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。 栅极设置在SOI衬底上。 电荷存储结构设置在栅极和SOI衬底之间。 底部电介质层设置在电荷存储层和SOI衬底之间。 第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。 第一导电型掺杂区域设置在第一导电型硅体层中，并且与栅极下方的第一导电型硅体层电连接。

公开(公告)号：US07715241B2

公开(公告)日：2010-05-11

申请号：US12056288

申请日：2008-03-27

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Sheng-Yu Wang ,  Cheng-Yen Shen

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Sheng-Yu Wang ,  Cheng-Yen Shen

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/14

摘要： A present invention relates to a method of erasing a P-channel non-volatile memory is provided. This P-channel non-volatile memory includes a select transistor and a memory cell connected in series and disposed on a substrate. In the method of erasing the P-channel non-volatile memory, holes are injected into a charge storage structure by substrate hole injection effect. Hence, the applied operational voltage is low, so the power consumption is lowered, and the efficiency of erasing is enhanced. As a result, an operational speed of the memory is accelerated, and the reliability of the memory is improved.

摘要翻译： 本发明涉及一种擦除P信道非易失性存储器的方法。 该P沟道非易失性存储器包括选择晶体管和串联连接并设置在基板上的存储单元。 在擦除P沟道非易失性存储器的方法中，通过衬底空穴注入效应将空穴注入电荷存储结构。 因此，施加的工作电压低，因此功耗降低，并且提高了擦除效率。 结果，加速了存储器的操作速度，并提高了存储器的可靠性。

公开(公告)号：US20100103430A1

公开(公告)日：2010-04-29

申请号：US12393953

申请日：2009-02-26

申请人： Meng-Tsan Tsai ,  Hsiang-Chieh Lee ,  Cheng-Kuang Lee ,  Yih-Ming Wang ,  Chun-Pin Chiang ,  Hsin-Ming Chen ,  Chih-Chung Yang

发明人： Meng-Tsan Tsai ,  Hsiang-Chieh Lee ,  Cheng-Kuang Lee ,  Yih-Ming Wang ,  Chun-Pin Chiang ,  Hsin-Ming Chen ,  Chih-Chung Yang

IPC分类号： G01B11/02 ,  G06F17/18 ,  G06F15/00

CPC分类号： G01B9/02091 ,  G01B9/02083

摘要： A method for analyzing mucosa structure with optical coherence tomography (OCT) is provided, and includes: (a) scanning a mucosa sample with optical coherence tomography; (b) choosing a lateral range from a two- or three-dimensional OCT image and analyzing all the A-scan intensity profiles in the lateral range; (c) calculating three indicators in each A-scan intensity profile, including the standard deviation for a certain depth range below the sample surface, the exponential decay constant of the spatial-frequency spectrum and the epithelium thickness under the condition that the basement membrane is identifiable; and (d) using the three indicators of each A-scan intensity profile within the lateral range to analyze the mucosa structure.

摘要翻译： 提供了一种用光学相干断层扫描（OCT）分析粘膜结构的方法，包括：（a）用光学相干断层扫描扫描粘膜样品; （b）选择二维或三维OCT图像的横向范围，并分析横向范围内的所有A扫描强度分布; （c）计算每个A扫描强度分布中的三个指标，包括样品表面以下一定深度范围的标准偏差，空间频谱和上皮厚度的指数衰减常数，基底膜为 可识别的 和（d）使用横向范围内每个A扫描强度分布的三个指标来分析粘膜结构。

公开(公告)号：US07682908B2

公开(公告)日：2010-03-23

申请号：US11163716

申请日：2005-10-28

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L27/108

CPC分类号： H01L29/792 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/115

摘要： A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.

摘要翻译： 公开了包括衬底，第一掺杂区，第二掺杂区，第三掺杂区，第一栅极结构和第二栅极结构的非易失性存储器。 掺杂区域设置在衬底中，第二掺杂区域设置在第一掺杂区域和第三掺杂区域之间。 第一栅极结构设置在第一掺杂区和第二掺杂区之间的衬底上。 第二栅极结构设置在第二掺杂区域和第三掺杂区域之间的衬底上，并且包括隧道电介质层，电荷捕获结构和从下向上的栅极。

公开(公告)号：US20100006924A1

公开(公告)日：2010-01-14

申请号：US12171301

申请日：2008-07-11

申请人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

发明人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

IPC分类号： H01L27/112

CPC分类号： H01L27/112 ,  H01L27/11206 ,  H01L27/11521

摘要： A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.

摘要翻译： 一种包括衬底，第一掺杂区域，第二掺杂区域，第三掺杂区域，第一介电层，选择栅极，第二介电层，第一沟道 ，提供第二通道和硅化物层。 第一掺杂区域，第二掺杂区域和第三掺杂区域设置在衬底中。 第一介电层设置在第一掺杂区和第二掺杂区之间的衬底上。 选择栅极设置在第一电介质层上。 第二介电层设置在第二掺杂区和第三掺杂区之间的衬底上。 硅化物层设置在第一掺杂区域，第二掺杂区域和第三掺杂区域上。 OTP-ROM通过发生在第二掺杂区域和第三掺杂区域之间的穿透效应来存储数据。