公开(公告)号：US10452397B2

公开(公告)日：2019-10-22

申请号：US15477022

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Abhishek R. Appu ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC: G06F9/30 ,  G06F12/0842 ,  G09G5/393 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190265765A1

公开(公告)日：2019-08-29

申请号：US16286166

申请日：2019-02-26

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Prasoonkumar Surti ,  Kiran C. Veernapu

IPC: G06F1/20 ,  G05B19/05

Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors. The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190251033A1

公开(公告)日：2019-08-15

申请号：US16277114

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Prasoonkumar Surti ,  Kamal Sinha ,  Kiran C. Veernapu ,  Balaji Vembu

IPC: G06F12/0888 ,  G06F13/40 ,  G06T1/60 ,  G06T1/20 ,  G06F13/42

CPC classification number: G06F12/0888 ,  G06F12/0895 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/6032 ,  G06F2213/0026 ,  G06T1/20 ,  G06T1/60

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190236026A1

公开(公告)日：2019-08-01

申请号：US16287781

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Kiran C. Veernapu

IPC: G06F12/1045 ,  G06T1/20 ,  G06T1/60 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/455 ,  G06F2212/657 ,  G06F2212/68 ,  G06T1/20 ,  G06T1/60

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline to bypass a memory access for the first virtual page based on the first page table entry, wherein the graphics pipeline is to read a field in the first page table entry to determine a value of the clear color.

公开(公告)号：US20190205163A1

公开(公告)日：2019-07-04

申请号：US15860708

申请日：2018-01-03

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Kamlesh Pillai ,  James Valerio ,  Joydeep Ray ,  Abhishek Appu

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/22 ,  G06T1/20

CPC classification number: G06F9/4881 ,  G06F9/22 ,  G06F9/54 ,  G06T1/20 ,  G06T15/005

Abstract: A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.

公开(公告)号：US10255109B2

公开(公告)日：2019-04-09

申请号：US15489062

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu

IPC: G06F9/50 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180308215A1

公开(公告)日：2018-10-25

申请号：US15493550

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Kiran C. Veernapu ,  Mohammed Tameem ,  Altug Koker ,  Abhishek R. Appu

IPC: G06T1/60 ,  G06F12/02 ,  G06F12/0875 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F12/023 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/455 ,  G06F2212/604 ,  G06T2210/08 ,  G06T2210/52

Abstract: A mechanism is described for facilitating dynamic cache allocation in computing devices in computing devices. A method of embodiments, as described herein, includes facilitating monitoring one or more bandwidth consumptions of one or more clients accessing a cache associated with a processor; computing one or more bandwidth requirements of the one or more clients based on the one or more bandwidth consumptions; and allocating one or more portions of the cache to the one or more clients in accordance with the one or more bandwidth requirements.

公开(公告)号：US20180307485A1

公开(公告)日：2018-10-25

申请号：US15493467

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Ramkumar Ravikumar ,  Kiran C. Veernapu ,  Prasoonkumar Surti ,  Vasanth Ranganathan

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F13/36 ,  G06F13/40

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to assemble a general register file (GRF) message and hold the GRF message in storage in a data port until all data for the GRF message is received. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180300177A1

公开(公告)日：2018-10-18

申请号：US15489062

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu

IPC: G06F9/50 ,  G06T1/20

CPC classification number: G06F9/505 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive a completion acknowledgment from the plurality of graphics processing units and in response to a determination that the workload is finished, to terminate one or more communication connections on the interconnect bridge. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180293702A1

公开(公告)日：2018-10-11

申请号：US15483059

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Prasoonkumar P. Surti ,  Kamal Sinha ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Bhushan M. Borole ,  Wenyin Fu

IPC: G06T1/60 ,  G06T15/00 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/005

Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.