公开(公告)号：US20190044044A1

公开(公告)日：2019-02-07

申请号：US15897712

申请日：2018-02-15

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Adel A. Elsherbini ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Hubert C. George ,  Stefano Pellerano

IPC: H01L39/02 ,  H01L39/22

Abstract: Embodiments of the present disclosure describe two approaches to providing flux bias line structures for superconducting qubit devices. The first approach, applicable to flux bias line structures that include at least one portion that terminates with a ground connection, resides in terminating such a portion with a ground connection that is electrically isolated from the common ground plane of a quantum circuit assembly. The second approach resides in providing a SQUID loop of a superconducting qubit device and a portion of the flux bias line structure over a portion of a substrate that is elevated with respect to other portions of the substrate. These approaches may be used or alone or in combination, and may improve grounding of and reduce crosstalk caused by flux bias lines in quantum circuit assemblies.

公开(公告)号：US20190043989A1

公开(公告)日：2019-02-07

申请号：US16017942

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/78 ,  H01L29/778 ,  H01L29/66 ,  H01L23/522 ,  H01L29/06

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

公开(公告)号：US20190043919A1

公开(公告)日：2019-02-07

申请号：US16012815

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Adel A. Elsherbini ,  Lester Lampert ,  James S. Clarke ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L27/18 ,  H01L39/22 ,  H01L49/02 ,  G06N99/00

Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.

公开(公告)号：US20240006499A1

公开(公告)日：2024-01-04

申请号：US17854242

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Kai Loon Cheong ,  Pooja Nath ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Charles C. Kuo ,  Nicole K. Thomas ,  Munzarin F. Qayyum ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Thoe Michaelos ,  David Kohen

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/6681

Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.

公开(公告)号：US20230420460A1

公开(公告)日：2023-12-28

申请号：US17847628

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Patrick Morrow ,  Quan Shi ,  Rohit Galatage ,  Nicole K. Thomas ,  Munzarin F. Qayyum ,  Jami A. Wiedemer ,  Gilbert Dewey ,  Mauro J. Kobrinsky ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L23/48

CPC classification number: H01L27/0924 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L23/481

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

公开(公告)号：US20230402507A1

公开(公告)日：2023-12-14

申请号：US17838637

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Rohit Galatage ,  Willy Rachmady ,  Cheng-Ying Huang ,  Jami A. Wiedemer ,  Munzarin F. Qayyum ,  Nicole K. Thomas ,  Patrick Morrow ,  Marko Radosavljevic ,  Mauro J. Kobrinsky

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit structure includes a second device stacked vertically above a first device. The first device includes (i) a first source or drain region, (ii) a first source or drain contact coupled to the first source or drain region, and (iii) a first layer comprising a first metal and first one or more semiconductor materials between at least a section of the first source or drain region and the first source or drain contact. The second device includes (i) a second source or drain region, (ii) a second source or drain contact coupled to the second source or drain region, and (iii) a second layer comprising a second metal and second one or more semiconductor materials between at least a section of the second source or drain region and the second source or drain contact. In an example, the first metal and the second metal are different.

公开(公告)号：US20230395678A1

公开(公告)日：2023-12-07

申请号：US17831802

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Munzarin F. Qayyum ,  Nicole K. Thomas ,  Jami A. Wiedemer ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Willy Rachmady ,  Cheng-Ying Huang ,  Rohit Galatage ,  Nitesh Kumar ,  Kai Loon Cheong ,  Venkata Vasiraju

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L27/092

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/41733 ,  H01L27/0924

Abstract: A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.

公开(公告)号：US11688735B2

公开(公告)日：2023-06-27

申请号：US17341559

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L29/775 ,  H10N69/00 ,  H01L27/088 ,  G06N10/00 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/778 ,  B82Y10/00

CPC classification number: H01L27/088 ,  G06N10/00 ,  H01L21/823456 ,  H01L29/66977 ,  H01L29/778 ,  H10N69/00 ,  B82Y10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

公开(公告)号：US20230197800A1

公开(公告)日：2023-06-22

申请号：US17556737

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Cheng-Ying Huang ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Patrick Morrow ,  Ashish Agrawal ,  Willy Rachmady ,  Nazila Haratipour ,  Seung Hoon Sung

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/40 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/401 ,  H01L29/0665 ,  H01L27/0922 ,  H01L29/66742

Abstract: Techniques are provided herein to form semiconductor devices having a non-reactive metal contact in an epi region of a stacked transistor configuration. An n-channel device may be located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A deep and narrow contact may be formed from either the frontside or the backside of the integrated circuit through the stacked source or drain regions. According to some embodiments, the contact is formed using a refractory metal or other non-reactive metal such that no silicide or germanide is formed with the epi material of the source or drain regions at the boundary between the contact and the source or drain regions.

公开(公告)号：US20230197777A1

公开(公告)日：2023-06-22

申请号：US17556748

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Cheng-Ying Huang ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Patrick Morrow ,  Ashish Agrawal ,  Willy Rachmady ,  Nazila Haratipour ,  Seung Hoon Sung ,  I-Cheng Tung ,  Christopher M. Neumann ,  Koustav Ganguly ,  Subrina Rafique

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices utilizing a metal fill in an epi region of a stacked transistor configuration. In one example, an n-channel device and the p-channel device may both be GAA transistors each having any number of nanoribbons extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. A metal fill may be provided around the source or drain region of the bottom semiconductor device to provide a high contact area between the highly conductive metal fill and the epitaxial material of that source or drain region. Metal fill may also be used around the top source or drain region to further improve conductivity throughout both of the stacked source or drain regions.