公开(公告)号：US20170046079A1

公开(公告)日：2017-02-16

申请号：US14823383

申请日：2015-08-11

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F9/3004 ,  G11C7/04 ,  G11C11/40626 ,  G11C11/4091

Abstract: A memory controller may receive a plurality of thermal profiles from a plurality of three-dimensional (3D)-stacked memory chips, where the plurality of thermal profiles include thermal profile data for the memory chips, where the thermal profile data includes a memory chip usage data and a location data for each of the memory chips, and where the memory chips include a first memory chip and a second memory chip. The memory controller may generate a first predicted memory chip usage data and location data by analyzing the usage data and location data of the thermal profile data. A second predicted memory chip usage data and location data may be generated. Based on the predicted memory chip, fractional memory chip read propensity data may be generated. The memory controller may distribute, according the first fractional memory chip read propensity distribution, memory chip read operations.

Abstract translation: 存储器控制器可以从多个三维（3D）堆叠的存储器芯片中接收多个热分布，其中多个热分布包括用于存储器芯片的热分布数据，其中热分布数据包括存储器芯片使用 数据和每个存储器芯片的位置数据，并且其中存储器芯片包括第一存储器芯片和第二存储器芯片。 存储器控制器可以通过分析热分布数据的使用数据和位置数据来产生第一预测的存储器芯片使用数据和位置数据。 可以生成第二预测的存储器芯片使用数据和位置数据。 基于预测的存储器芯片，可以产生分数存储器芯片读取倾向数据。 存储器控制器可以根据第一分数存储器芯片读取倾向分布来分配存储器芯片读取操作。

公开(公告)号：US20170031787A1

公开(公告)日：2017-02-02

申请号：US15291352

申请日：2016-10-12

Applicant: International Business Machines Corporation

Inventor： Timothy J. Dell ,  Saravanan Sethuraman ,  Diyanesh B. C. Vidyapoornachary

IPC: G06F11/16 ,  G06F3/06 ,  G06F11/20 ,  G06F12/1009

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/1068 ,  G06F11/1666 ,  G06F11/2056 ,  G06F11/2069 ,  G06F11/2087 ,  G06F11/2094 ,  G06F12/1009 ,  G06F2201/805 ,  G06F2201/85 ,  G06F2201/86 ,  G11C29/44 ,  G11C29/52 ,  G11C29/70 ,  G11C29/76 ,  G11C29/886 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.

Abstract translation: 根据一个方面，用于存储器系统中的读取功能的性能优化的方法包括在存储器系统处接收包括目标数据的逻辑地址的读取请求。 存储器系统包括主存储器和反映主存储器的备份存储器。 该方法还包括在故障监视表中搜索与接收到的逻辑地址相对应的条目。 故障监视表包括指示主存储器和备用存储器中所识别的存储器故障事件的物理位置的多个条目。 基于找到对应于所接收的逻辑地址的条目，该方法还包括选择主存储器和备用存储器中的一个以检索目标数据。 选择是基于故障监视表的内容。

公开(公告)号：US09535784B2

公开(公告)日：2017-01-03

申请号：US14623706

申请日：2015-02-17

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Timothy J. Dell ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

IPC: G01R31/28 ,  G06F11/10 ,  G06F11/28 ,  H03M13/29 ,  G06F11/20

CPC classification number: G06F11/10 ,  G06F11/1048 ,  G06F11/2017 ,  G06F11/28 ,  H03M13/29

Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

Abstract translation: 本发明的示例性实施例公开了一种用于监视第一纠错码（ECC）设备的方法和系统，用于如果第一ECC设备开始失败或失败，则用第二ECC设备故障并替换第一ECC设备。 在一个步骤中，如果超过指定数量的可校正错误或者发生不可校正的错误，则示例性实施例对ECC设备执行环回测试。 在另一步骤中，示例性实施例用通过环回测试的ECC设备替代了对环回测试失败的ECC设备。

公开(公告)号：US20160161962A1

公开(公告)日：2016-06-09

申请号：US15042751

申请日：2016-02-12

Applicant: International Business Machines Corporation

Inventor： Vijay A. Mathiyalagan ,  Siva Rama K. Pullelli ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G05F1/625 ,  H01L23/50 ,  G11C5/14 ,  H01L25/065

CPC classification number: G05F1/625 ,  G11C5/063 ,  G11C5/14 ,  G11C8/12 ,  H01L23/50 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure includes a three dimensional (3D) integrated device comprising a first die having a first supply line and a second die having a second supply line, a power header, and voltage selection logic. The power header is connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic is connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line.

公开(公告)号：US09361195B2

公开(公告)日：2016-06-07

申请号：US14538966

申请日：2014-11-12

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G06F12/00 ,  G06F13/00 ,  G06F11/20 ,  G11C5/02 ,  G06F11/14

CPC classification number: G06F11/2058 ,  G06F11/1456 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2069 ,  G06F11/3037 ,  G06F11/3058 ,  G06F2201/84 ,  G11C5/02 ,  G11C7/04 ,  G11C29/028 ,  G11C29/783 ,  G11C29/83 ,  G11C2029/0409 ,  G11C2029/5002

Abstract: A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.

Abstract translation: 三维堆叠存储器中的镜像方法包括从多个存储器芯片接收多个热剖面图。 该方法还包括将存储器芯片的第一排列列表中的多个存储器芯片排列为多个热分布的函数，并且基于第一排列的存储芯片列表从多个存储器芯片形成第一组存储器芯片 。 该方法还包括基于第一排列的存储器芯片列表从不同于第一组存储器芯片的多个存储器芯片形成第二组存储器芯片。 该方法还包括将来自第一组存储器芯片的第一存储器芯片和来自第二组存储器芯片的第二存储器芯片配对，并且镜像存储器芯片的配对。

公开(公告)号：US09305618B2

公开(公告)日：2016-04-05

申请号：US14168102

申请日：2014-01-30

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Carlos A. Fernandez ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

IPC: G06F12/00 ,  G11C7/10 ,  G11C8/16 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C7/1075 ,  G06F11/1048 ,  G11C7/1045 ,  G11C8/16 ,  G11C2029/0411 ,  G11C2207/2209

Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

公开(公告)号：US20150370711A1

公开(公告)日：2015-12-24

申请号：US14573970

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  David M. Daly ,  Robert K. Montoye ,  Saravanan Sethuraman ,  Diyanesh B. Chinnakkonda Vidyapoornachary

IPC: G06F12/08 ,  G06F9/455

CPC classification number: G06F12/0811 ,  G06F3/00 ,  G06F9/45558 ,  G06F9/50 ,  G06F12/0833 ,  G06F13/1673 ,  G06F13/4045 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/62

Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.

Abstract translation: 公开了能够分配要由高速缓存功能控制器（OFC）使用的存储器缓冲器的高速缓存部分来执行“主线”数据的处理功能的装置和方法。 特定方法可以包括在存储器缓冲器处接收来自存储器控制器的用于分配存储器缓冲器的高速缓存部分的请求。 该方法还可以包括由存储器缓冲器的高速缓存功能控制器（OFC）获取存储器缓冲器的所请求的高速缓存部分。 该方法还可以包括由OFC执行对存储在存储器缓冲器的高速缓存部分上的数据的处理功能。

公开(公告)号：US20150332736A1

公开(公告)日：2015-11-19

申请号：US14276025

申请日：2014-05-13

Applicant: International Business Machines Corporation

Inventor： Venkatraghavan Bringivijayaraghavan ,  Saurabh Chadha ,  Abhijit Saurabh ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G11C5/14 ,  G06F11/16 ,  G06F13/28 ,  G06F11/30 ,  G06F13/40 ,  G06F13/16 ,  G11C5/06 ,  G06F11/07

CPC classification number: G06F3/06 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/0727 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2017 ,  G06F11/2092 ,  G06F11/3027 ,  G06F11/3034 ,  G06F13/1684 ,  G06F13/287 ,  G06F13/4068 ,  G11C5/06 ,  G11C5/148 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.

公开(公告)号：US20150213853A1

公开(公告)日：2015-07-30

申请号：US14168102

申请日：2014-01-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Edgar R. Cordero ,  Carlos A. Fernandez ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

IPC: G11C7/10

CPC classification number: G11C7/1075 ,  G06F11/1048 ,  G11C7/1045 ,  G11C8/16 ,  G11C2029/0411 ,  G11C2207/2209

Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

公开(公告)号：US20150127899A1

公开(公告)日：2015-05-07

申请号：US14074171

申请日：2013-11-07

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Carlos A. Fernandez ,  Joab D. Henderson ,  William P. Hovis ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

IPC: G11C11/406

CPC classification number: G11C11/40603 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

Abstract: A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.

Abstract translation: 从存储器控制器接收到刷新命令。 启动包含多个段刷新的可中断刷新。 片段刷新由中断边界分隔。 执行片段刷新之前接收到一条命令。 执行第一命令并且在第一中断边界处延迟执行第一段刷新。 或者，从存储器控制器接收要执行的第一数量的段刷新。 接收到的第一个段刷新数被执行。 从存储器控制器接收第二数量的片段刷新以执行。 接收到的第二数量的段刷新被执行。 在执行第一段段刷新和执行第二段段刷新之间不执行段刷新。