公开(公告)号：US10381431B2

公开(公告)日：2019-08-13

申请号：US15797848

申请日：2017-10-30

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L27/11507 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/283 ,  H01B3/10

Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

公开(公告)号：US10332957B2

公开(公告)日：2019-06-25

申请号：US15198800

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Vijay Narayanan ,  Adam M. Pyzyna

IPC: H01L49/02

Abstract: A layered structure including a tri-stack dielectric layer and a plurality of metal layers insulated from each other by the tri-stack dielectric layer. The plurality of metal layers includes a set of first-type metal layers and a set of second-type metal layers. An adjacent pair of the plurality of metal layers includes a first-type metal layer and a second-type metal layer. The tri-stack dielectric layer includes a first tri-stack layer including Al2O3, a second tri-stack layer including HfO2; and a third tri-stack layer including Al2O3.

公开(公告)号：US10319818B2

公开(公告)日：2019-06-11

申请号：US15797774

申请日：2017-10-30

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L29/12 ,  H01L29/06 ,  H01L27/085 ,  H01L23/52

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

公开(公告)号：US10304936B2

公开(公告)日：2019-05-28

申请号：US15146325

申请日：2016-05-04

Applicant: International Business Machines Corporation

Inventor： Nicolas J. Loubet ,  Sanjay C. Mehta ,  Vijay Narayanan ,  Muthumanickam Sankarapandian

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

Abstract: A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrateforming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystallize the high-k dielectric layer.

公开(公告)号：US20190131407A1

公开(公告)日：2019-05-02

申请号：US15797774

申请日：2017-10-30

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L29/12 ,  H01L23/52 ,  H01L27/085 ,  H01L29/06

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

公开(公告)号：US10249543B2

公开(公告)日：2019-04-02

申请号：US15795413

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US10249540B2

公开(公告)日：2019-04-02

申请号：US15813958

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  ChoongHyun Lee ,  Vijay Narayanan

IPC: H01L29/76 ,  H01L29/94 ,  H01L21/8238 ,  H01L21/324 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/161 ,  H01L29/16 ,  H01L29/10 ,  H01L21/28 ,  H01L21/02

Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.

公开(公告)号：US20190027572A1

公开(公告)日：2019-01-24

申请号：US16139795

申请日：2018-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L29/49 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/30608 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.

公开(公告)号：US20180350935A1

公开(公告)日：2018-12-06

申请号：US16040978

申请日：2018-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee ,  Vijay Narayanan ,  Koji Watanabe

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/4908 ,  B82Y10/00 ,  H01L21/28088 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

Abstract: A method is presented for forming a nanosheet structure having a uniform threshold voltage (Vt). The method includes forming a conductive barrier surrounding a nanosheet, forming a first work function conducting layer over the conductive barrier layer, and forming a conducting layer adjacent the first work function conducting layer, the conducting layer defining a first region and a second region. The method further includes forming a second work function conducting layer over the second region of the conducting layer to compensate for threshold voltage offset between the first and second regions of the conducting layer.

公开(公告)号：US20180308844A1

公开(公告)日：2018-10-25

申请号：US16012032

申请日：2018-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan ,  John Rozen

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8258

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/8258 ,  H01L27/092

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.