公开(公告)号：US11899599B2

公开(公告)日：2024-02-13

申请号：US17527929

申请日：2021-11-16

Applicant: INTEL CORPORATION

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Doron Rajwan ,  Hisham Abu Salah ,  Ariel Gur ,  Guy M. Therien ,  Russell J. Fenger

IPC: G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F1/3234 ,  G06F9/44 ,  G06F9/4401

CPC classification number: G06F13/24 ,  G06F1/329 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/44 ,  G06F9/4411

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US11815979B2

公开(公告)日：2023-11-14

申请号：US16633120

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Yoni Aizik ,  Esfir Natanzon ,  Nir Rosenzweig ,  Nadav Shulman ,  Bart Plackle

IPC: G06F1/329 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F9/4893

Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

公开(公告)号：US20230359263A1

公开(公告)日：2023-11-09

申请号：US18353790

申请日：2023-07-17

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/324 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3206 ,  G06F1/26

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3203

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

公开(公告)号：US11789516B2

公开(公告)日：2023-10-17

申请号：US17440688

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Chen Ranel ,  Christopher J. Lake ,  Hem Doshi ,  Ido Melamed ,  Vijay Degalahal ,  Yevgeni Sabin ,  Reena Patel ,  Yoav Ben-Raphael ,  Nimrod Angel ,  Efraim Rotem ,  Shaun Conrad ,  Tomer Ziv ,  Nir Rosenzweig ,  Esfir Natanzon ,  Yoni Aizik ,  Arik Gihon ,  Natanel Abitan

IPC: G06F1/00 ,  G06F1/324

CPC classification number: G06F1/324

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

公开(公告)号：US11650648B2

公开(公告)日：2023-05-16

申请号：US16914029

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Maximilian Domeika ,  Soethiha Soe ,  James Hermerding, II ,  Zhongsheng Wang ,  Wessam Elhefnawy ,  Efraim Rotem ,  Christopher Joseph Binns

IPC: G06F1/32 ,  G06F11/30 ,  G06K9/62 ,  G06F1/3212 ,  G06F1/3296

CPC classification number: G06F1/3212 ,  G06F1/3296 ,  G06F11/3062 ,  G06F11/3075 ,  G06K9/6262

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve computing device power management. An example apparatus includes a usage classifier to classify usage of a computing system, a low battery probability determiner to determine a probability of the computing system operating with a low battery capacity based on the classification, a policy reward determiner to determine an adjustment of a policy based on at least one of the classification or the probability, and determine a battery capacity of the computing system in response to the adjustment, and a policy adjustor to adjust the policy in response to the battery capacity satisfying a threshold.

公开(公告)号：US11593544B2

公开(公告)日：2023-02-28

申请号：US16629600

申请日：2017-08-23

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Boris Mishori ,  Eran Dagan

IPC: G06F30/00 ,  G06F30/34 ,  G06F1/3296 ,  G06F15/78

Abstract: In one embodiment, a field programmable gate array (FPGA) includes: at least one programmable logic circuit to execute a function programmed with a bitstream; a self-test circuit to execute a self-test at a first voltage, the self-test and the first voltage programmed with first metadata associated with the bitstream, the self-test including at least one critical path length of the function; and a power controller to identify an operating voltage for the at least one programmable logic circuit based at least in part on the execution of the self-test at the first voltage.

公开(公告)号：US11221857B2

公开(公告)日：2022-01-11

申请号：US16388670

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Paul S. Diefenbaugh ,  Anil Aggarwal ,  Andrew D. Henroid ,  Jeremy J. Shrall ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Eliezer Weissmann

IPC: G06F1/00 ,  G06F11/30 ,  G06F9/4401 ,  G06F16/22 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/44 ,  G06F9/445 ,  G06F1/28 ,  G06F1/3234 ,  G06F11/36 ,  G06F1/26 ,  G06F9/22 ,  G06F11/34 ,  G06F9/30 ,  G06F1/20 ,  G06F15/78 ,  G06F1/32 ,  G06F9/38 ,  G06F119/06

Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

公开(公告)号：US11182315B2

公开(公告)日：2021-11-23

申请号：US15430345

申请日：2017-02-10

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Doron Rajwan ,  Hisham Abu Salah ,  Ariel Gur ,  Guy M. Therien ,  Russell J. Fenger

IPC: G06F13/24 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30 ,  G06F9/44 ,  G06F9/4401 ,  G06F1/3234

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US11157329B2

公开(公告)日：2021-10-26

申请号：US16523009

申请日：2019-07-26

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Hisham Abu-Salah ,  Nir Rosenzweig ,  Efraim Rotem

IPC: G06F1/08 ,  G06F1/324 ,  G06F9/50

Abstract: A processor comprises multiple cores and power management control logic to determine (a) a preliminary frequency for each of the cores and (b) a maximum frequency, based on the preliminary frequencies. The power management control logic is also to determines a dynamic tuning frequency, based on the maximum frequency and a reduction factor. In response to the dynamic tuning frequency for a selected core being greater than the preliminary frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the dynamic tuning frequency. In response to the preliminary frequency for the selected core being greater than the dynamic tuning frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the preliminary frequency. Other embodiments are described and claimed.

公开(公告)号：US20200278914A1

公开(公告)日：2020-09-03

申请号：US16647563

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： HISHAM ABU SALAH ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jacob Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.