公开(公告)号：US09245941B2

公开(公告)日：2016-01-26

申请号：US14140807

申请日：2013-12-26

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Mankoo Lee ,  Dipankar Pramanik

IPC: H01L21/28 ,  H01L49/02 ,  H01L21/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L21/02156 ,  H01L21/02186 ,  H01L21/02356 ,  H01L21/28088 ,  H01L21/28229 ,  H01L27/1085 ,  H01L2924/0134 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/10671

Abstract: A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

Abstract translation: 可以使用YBCO基导电材料作为电极，其可以与诸如高k电介质的电介质接触。 或者，具有窄导带的材料可以用作可以与诸如高k电介质的电介质接触的电极。 通过将电介质与YBCO基电极的带隙或窄带导电材料电极的带隙对准，例如，电介质的导带最小值落入基于YBCO的电极的带隙之一或 窄带导电材料可以减少通过电介质的热离子泄漏，因为电极中激发的电子或空穴需要较高的热激发能量以克服通过电介质层之前的带隙。

公开(公告)号：US09240236B1

公开(公告)日：2016-01-19

申请号：US14577613

申请日：2014-12-19

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Dipankar Pramanik

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50 ,  G11C29/02

CPC classification number: G11C29/02 ,  G11C13/0007 ,  G11C29/50 ,  G11C2013/0083 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1641

Abstract: Provided are method for determining switching conditions for production memory cells based on dopant flux during set and reset operations. One group of test memory cells, which are representative of the production memory cells, is subjected to a prolonged application of a set voltage, while another group is subjected to a prolonged application of a reset voltage. Different durations may be used for different cells in each group. A dopant concentration profile of a test component in each cell is determined for both groups. One cell from each group may be identified such that the changes in the dopant concentration profiles in these two identified cells are complementary. The profile complementarity indicates that these two identified cells had a similar dopant flux during voltage applications. Durations of set and reset voltage applications for these two cells may be used to determine switching conditions for production memory cells.

Abstract translation: 提供了在设置和复位操作期间基于掺杂剂通量确定生产存储器单元的切换条件的方法。 代表生产存储器单元的一组测试存储单元经受长时间施加的设定电压，而另一组经受长时间应用复位电压。 不同的持续时间可以用于每组中的不同细胞。 确定每个细胞中测试组分的掺杂浓度分布。 可以鉴定每个组中的一个细胞，使得这两个鉴定的细胞中的掺杂剂浓度分布的变化是互补的。 配置互补性表明这两个识别的电池在电压施加期间具有相似的掺杂剂通量。 这两个单元的设定和复位电压应用的持续时间可用于确定生产存储单元的切换条件。

公开(公告)号：US09099488B2

公开(公告)日：2015-08-04

申请号：US14134291

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Sandip Niyogi ,  Dipankar Pramanik

IPC: H01L29/66 ,  H01L21/66

CPC classification number: H01L29/66181 ,  G01N27/002 ,  H01L22/14 ,  H01L22/20

Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. Surface treatments can be inserted at three possible steps during the formation of the MOSCAP structures. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

Abstract translation: 使用光刻图案化的金属栅极高k电容器结构使用组合工作流程提取门功函数。 氧化物梯田，以及用于金属沉积的高生产率组合工艺流程可为高性能逻辑晶体管提供最佳的高k栅介质和金属栅极解决方案。 在形成MOSCAP结构期间，可以以三个可能的步骤插入表面处理。 高生产率组合技术可以为PMOS和NMOS晶体管的给定高k介质金属栅极叠层提供有效的工作函数的评估，这对于识别和选择正确的材料至关重要。

公开(公告)号：US09076523B2

公开(公告)日：2015-07-07

申请号：US13714173

申请日：2012-12-13

Applicant: Intermolecular, Inc.

Inventor： Mankoo Lee ,  Tony Chiang ,  Dipankar Pramanik

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L29/785 ,  H01L29/868 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.

Abstract translation: 非线性电流响应电路可用于嵌入式电阻式存储单元，以降低功耗，同时提高存储器阵列的可靠性。 非线性电流响应电路可以包括两个背靠背泄漏的PIN二极管，两个并联的反向PIN二极管，两个背靠背的齐纳二极型金属氧化物二极管或者二极管开关元件，以及用于待机功率降低的限流电阻 低电压区域。 此外，所提出的基于1T2D1R方案的嵌入式ReRAM实现方法可以集成到先进的FEOL工艺技术中，包括用于实现高度紧凑的单元密度的立柱晶体管和/或3D鳍状场效应晶体管（FinFET）。

公开(公告)号：US09054307B2

公开(公告)日：2015-06-09

申请号：US14317155

申请日：2014-06-27

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: G11C13/00 ,  G11C7/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

Abstract translation: 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由过渡金属的合金形成的限流层。 这种合金的一些实例包括还可以包括镍，铝和/或硅的含铬合金。 其它实例包括也可以包括硅和碳的组合或铝和氮的组合的含钽和/或钛的合金。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温处理时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压为至少约8V。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

公开(公告)号：US20150123071A1

公开(公告)日：2015-05-07

申请号：US14598499

申请日：2015-01-16

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的存储器件和方法。 在一个实施例中，一种用于制造电阻式开关存储器件的方法包括在设置在衬底上的下电极上沉积金属层，并将该金属层暴露于活性氧源，同时将衬底加热至约300 约600℃，并且在氧化过程中从金属层的上部形成金属氧化物层。 下部电极含有硅材料，金属层含有铪或锆。 在氧化处理之后，该方法还包括将衬底加热至大于600℃至约850℃的范围内的退火温度，同时在硅化期间从金属层的下部形成金属硅化物层 处理。

公开(公告)号：US09023739B2

公开(公告)日：2015-05-05

申请号：US13722624

申请日：2012-12-20

Applicant: Intermolecular, Inc.

Inventor： Ed Korczynski ,  Dipankar Pramanik

IPC: H01L21/26 ,  H05B1/02 ,  H01L21/268 ,  H01L21/67

CPC classification number: H05B1/0233 ,  H01L21/2686 ,  H01L21/67115 ,  H01L21/67253

Abstract: Methods and apparatus are described that allow the investigation of process variables used in RTP systems to be varied in a combinatorial manner across a plurality of site-isolated regions designated in the surface of a substrate. The methods and apparatus allow process variables such as power, dwell time, light source, cooling gas composition, cooling gas flow rate, reactive gas composition, reactive gas flow rate, and substrate support temperature and the like to be investigated.

Abstract translation: 描述了允许在RTP系统中使用的过程变量的研究以组合方式跨越在衬底的表面中指定的多个位置隔离区域进行的调查的方法和装置。 该方法和装置允许研究诸如功率，停留时间，光源，冷却气体组成，冷却气体流速，反应气体组成，反应气体流速和衬底支撑温度等过程变量。

公开(公告)号：US08987865B2

公开(公告)日：2015-03-24

申请号：US14288003

申请日：2014-05-27

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Mankoo Lee

IPC: H01L29/8605 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/14 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Abstract translation: 提供了并入电阻式开关存储单元或装置中以形成具有改进的器件性能和寿命的存储器件的电阻器结构。 电阻器结构可以是设计成减小流过存储器件的最大电流的两端结构。 还提供了一种用于制造这种存储器件的方法。 该方法包括沉积电阻器结构并沉积存储器件的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联设置以限制存储器件的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器件的开关规范的期望的器件开关电流水平是非常有用的。 存储器件可以形成为可用于各种电子器件的大容量非易失性存储器集成电路的一部分。

公开(公告)号：US20150017780A1

公开(公告)日：2015-01-15

申请号：US14504620

申请日：2014-10-02

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/16 ,  H01L27/2463 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: A nonvolatile resistive memory element includes one or more novel oxygen isolation structures that protect the resistive switching material of the memory element from oxygen migration. One such oxygen isolation structure comprises an oxygen barrier layer that isolates the resistive switching material from other portions of the resistive memory device during fabrication and/or operation of the memory device. Another such oxygen isolation structure comprises a sacrificial layer that reacts with unwanted oxygen migrating toward the resistive switching material during fabrication and/or operation of the memory device.

Abstract translation: 非易失性电阻存储元件包括一个或多个新颖的氧隔离结构，其保护存储元件的电阻开关材料免于氧迁移。 一个这样的氧隔离结构包括氧阻隔层，其在制造和/或操作存储器件期间将电阻性开关材料与电阻式存储器件的其它部分隔离。 另一种这样的氧隔离结构包括牺牲层，其在存储器件的制造和/或操作期间与向电阻开关材料迁移的不想要的氧化反应。

公开(公告)号：US08895390B2

公开(公告)日：2014-11-25

申请号：US13828665

申请日：2013-03-14

Applicant: Intermolecular Inc.

Inventor： Dipankar Pramanik

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/74 ,  H01L45/00 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L21/0332 ,  H01L21/32139 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1641

Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的存储器件和方法。 在一个实施例中，提供了一种用于形成具有纹理电极的存储器件的方法，包括在设置在衬底上的下电极上形成氧化硅层，在氧化硅层上形成金属颗粒，其中金属颗粒分开设置 彼此在氧化硅层上。 该方法还包括在金属颗粒之间蚀刻，同时去除氧化硅层的一部分并在下电极内形成槽，通过湿法蚀刻工艺除去金属颗粒和剩余的氧化硅层，同时显露由设置在 下电极，在槽内和下电极的峰上形成金属氧化物膜堆叠，并在金属氧化物膜堆叠上形成上电极。