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    Methods for Forming Ferroelectric Phases in Materials and Devices Utilizing the Same
    1.
    发明申请
    Methods for Forming Ferroelectric Phases in Materials and Devices Utilizing the Same 审中-公开
    使用它的材料和器件中形成铁电相的方法

    公开(公告)号：US20160181091A1

    公开(公告)日：2016-06-23

    申请号：US14576853

    申请日：2014-12-19

    Applicant: Intermolecular, Inc.

    Inventor： Sandip Niyogi ,  Sergey Barabash ,  Federico Nardi ,  Dipankar Pramanik

    IPC: H01L21/02

    CPC classification number: H01L29/516

    Abstract: Embodiments provided herein describe systems and methods for forming ferroelectric materials. A trench body may be provided. A trench may be formed in the trench body. A dielectric material and a filler material may be deposited within the trench. The filler material may be heated such that a stress is exerted on the dielectric material before the dielectric material is heated to generate a ferroelectric phase within the dielectric material. A non-contiguous layer may be formed above a substrate. A second layer including a high-k dielectric material may be formed above the first layer. The high-k dielectric material may be heated to generate a ferroelectric phase within the high-k dielectric material.

    Abstract translation: 本文提供的实施例描述了用于形成铁电材料的系统和方法。 可以提供沟槽体。 可以在沟槽体中形成沟槽。 介电材料和填充材料可以沉积在沟槽内。 填充材料可以被加热，使得在介电材料被加热之前在电介质材料上施加应力以在电介质材料内产生铁电相。 可以在衬底之上形成不连续的层。 可以在第一层之上形成包括高k电介质材料的第二层。 可以加热高k介电材料以在高k电介质材料内产生铁电相。

    Capacitors including inner and outer electrodes
    3.
    发明授权
    Capacitors including inner and outer electrodes 有权
    电容器包括内外电极

    公开(公告)号：US09224799B2

    公开(公告)日：2015-12-29

    申请号：US14145117

    申请日：2013-12-31

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: H01L49/02 ,  H01L27/08 ,  H01L29/66 ,  H01L29/94 ,  H01L27/108

    CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L29/66181 ,  H01L29/94

    Abstract: Provided are capacitor stacks for use in integrated circuits and methods of fabricating these stacks. A capacitor stack includes a dielectric layer and one or two inner electrode layers, such as a positive inner electrode layer and a negative inner electrode layer. The inner electrode layers directly interface the dielectric layer. The stack may also include outer electrode layers. The inner electrode layers are either chemically stable or weakly chemically unstable, while in contact with the dielectric layer based on the respective phase diagrams. Furthermore, the electron affinity of the positive inner electrode layer may be less than the electron affinity of the dielectric layer. The sum of the electron affinity and bandgap of the negative inner electrode layer may be less than that of the dielectric layer. In some embodiments, inner electrode layers are formed from heavily doped semiconducting materials, such as gallium arsenide or gallium aluminum arsenide.

    Abstract translation: 提供用于集成电路的电容器堆叠以及制造这些堆叠的方法。 电容器堆叠包括电介质层和一个或两个内部电极层，例如正的内部电极层和负的内部电极层。 内部电极层直接与介电层接触。 堆叠还可以包括外部电极层。 内部电极层是化学稳定的或弱的化学不稳定的，同时基于相应的相图与介电层接触。 此外，正内电极层的电子亲和力可能小于电介质层的电子亲和力。 负的内电极层的电子亲和力和带隙的总和可以小于电介质层的电子亲和力。 在一些实施例中，内部电极层由重掺杂的半导体材料形成，例如砷化镓或砷化镓铝。

    Method of depositing films with narrow-band conductive properties
    6.
    发明授权
    Method of depositing films with narrow-band conductive properties 有权
    沉积窄带导电性能的方法

    公开(公告)号：US09105704B2

    公开(公告)日：2015-08-11

    申请号：US13722931

    申请日：2012-12-20

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: H01L21/3065 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/768

    CPC classification number: H01L29/78 ,  H01L21/28255 ,  H01L21/3105 ,  H01L21/76823 ,  H01L21/76826

    Abstract: Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.

    Abstract translation: 具有窄杂质导带的导电材料可以减少高能量激发的数量，并且可以通过一系列等离子体处理来制备。 例如，电介质层可以暴露于第一等离子体环境以形成空位，并且随后将空位形成的电介质层暴露于第二等离子体环境以用替代杂质填充空位。

    MoOx-based resistance switching materials
    9.
    发明授权
    MoOx-based resistance switching materials 有权
    基于MoOx的电阻开关材料

    公开(公告)号：US08907314B2

    公开(公告)日：2014-12-09

    申请号：US13727958

    申请日：2012-12-27

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

    IPC: H01L29/02 ,  H01L45/00

    CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641

    Abstract: Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo13O33, Mo4O11, Mo17O47, Mo8O23, or Mo9O26. An electric field can be established across the switching layers, for example, by applying a set or reset voltage. The electric field can cause movement of the oxygen charges, e.g., O2− ions, changing the composition profile of the switching layers, forming bistable states, including a high resistance state with MoO3 and a low resistance state with MoOx (x

    Abstract translation: 氧化钼可用于在电阻式存储器件中形成开关元件。 氧与钼的原子比可以在2和3之间。氧化钼存在于各种Magneli相中，例如Mo13O33，Mo4O11，Mo17O47，Mo8O23或Mo9O26。 可以跨开关层建立电场，例如通过施加置位或复位电压。 电场可导致氧电荷的移动，例如O 2离子，改变开关层的组成分布，形成双稳态，包括具有MoO 3的高电阻状态和具有MoO x（x <3）的低电阻状态）。

    Flourine-Stabilized Interface
    10.
    发明申请
    Flourine-Stabilized Interface 有权
    面粉稳定界面

    公开(公告)号：US20140183666A1

    公开(公告)日：2014-07-03

    申请号：US13728957

    申请日：2012-12-27

    Applicant: INTERMOLECULAR, INC.

    Inventor： Dipankar Pramanik

    IPC: H01L29/40 ,  H01L29/423

    CPC classification number: H01L29/401 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/785 ,  H01L29/7866

    Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-κ dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.

    Abstract translation: 公开了一种形成具有氟稳定的半导体衬底表面的电子器件的方法。 在一个示例性实施例中， 介电材料与半导体衬底上含氟层一起形成。 随后的退火使氟迁移到半导体的表面（例如，硅，锗或硅 - 锗）。 半导体氧化物的薄中间层也可以存在于半导体表面。 含氟层可以包含由WF6的ALD和SiH 4前体气体形成的含F的WSix。 可以提供精确量的F，其足以与半导体衬底的表面上的基本上所有的悬空半导体原子结合，并且足以使基本上位于半导体衬底的表面处的所有氢原子置换。

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