公开(公告)号：US20080299733A1

公开(公告)日：2008-12-04

申请号：US11969412

申请日：2008-01-04

申请人： Patrick Press ,  Frank Wirbeleit ,  Joe Bloomquist ,  Kai Frohberg ,  Thomas Feudel

发明人： Patrick Press ,  Frank Wirbeleit ,  Joe Bloomquist ,  Kai Frohberg ,  Thomas Feudel

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature having a side surface and a top surface is formed over the substrate. A material layer is formed over the substrate. The material layer covers at least the side surface of the feature. An ion implantation process is performed to create an ion-implanted portion in the material layer. An etch process adapted to remove the ion-implanted portion at a greater etch rate than other portions of the material layer is performed.

摘要翻译： 形成半导体结构的方法包括提供半导体衬底。 具有侧表面和顶表面的特征形成在衬底上。 材料层形成在衬底上。 材料层至少覆盖该特征的侧表面。 进行离子注入工艺以在材料层中产生离子注入部分。 执行适于以比材料层的其它部分更高的蚀刻速率去除离子注入部分的蚀刻工艺。

公开(公告)号：US20080057705A1

公开(公告)日：2008-03-06

申请号：US11696226

申请日：2007-04-04

申请人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

发明人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/0273 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76823 ,  H01L21/76825

摘要： By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.

摘要翻译： 通过在蚀刻掩模内形成用于各向异性蚀刻工艺的导电材料，用于图案化金属化结构的电介质层中的诸如通路的开口，因为过量电荷可能横向分布，所以可以减小电弧事件的概率。 例如，可以形成附加的牺牲导电层，或者可以以导电材料的形式提供抗反射涂层（ARC），以获得横向电荷分布。

公开(公告)号：US20080026492A1

公开(公告)日：2008-01-31

申请号：US11695657

申请日：2007-04-03

申请人： Ralf Richter ,  Frank Feustel ,  Thomas Werner ,  Kai Frohberg

发明人： Ralf Richter ,  Frank Feustel ,  Thomas Werner ,  Kai Frohberg

IPC分类号： H01L21/469 ,  H01L21/66

CPC分类号： H01L21/02074 ,  H01L21/0209 ,  H01L21/02096

摘要： By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.

摘要翻译： 通过在中间制造阶段提供保护层，可以实现相对于颗粒污染和表面腐蚀的增加的表面保护。 在一些说明性实施例中，保护层可以在电测试过程中使用，其中相应的接触部分通过保护层接触，从而在相应的测量过程中显着地减少颗粒污染。

公开(公告)号：US20070077749A1

公开(公告)日：2007-04-05

申请号：US11423900

申请日：2006-06-13

申请人： Kai Frohberg ,  Katja Huy ,  Volker Kahlert

发明人： Kai Frohberg ,  Katja Huy ,  Volker Kahlert

IPC分类号： H01L21/4763

CPC分类号： C23C14/046 ,  H01L21/76843 ,  H01L21/76865

摘要： By performing a re-sputter process during the formation of a barrier layer for a contact opening in a tungsten-based process, the reliability of the tungsten deposition, as well as the performance of the resulting contact plug, may be enhanced. During the re-sputtering process, a thickness of the titanium-based barrier layer may be reduced at the contact bottom, while at the same time the material is re-condensed on critical lower sidewall portions of the contact opening.

摘要翻译： 通过在形成钨基工艺中的接触开口的阻挡层的过程中进行再溅射工艺，可以提高钨沉积的可靠性以及所得到的接触塞的性能。 在再溅射过程中，钛基阻挡层的厚度可以在接触底部减小，同时材料在接触开口的临界下侧壁部分上再凝结。

公开(公告)号：US20130189822A1

公开(公告)日：2013-07-25

申请号：US13357285

申请日：2012-01-24

申请人： Kai Frohberg ,  Torsten Huisinga ,  Katrin Reiche

发明人： Kai Frohberg ,  Torsten Huisinga ,  Katrin Reiche

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/823475 ,  H01L29/7833

摘要： Methods are provided for fabricating integrated circuits that include forming first and second spaced apart gate structures overlying a semiconductor substrate, and forming first and second spaced apart source/drain regions in the semiconductor substrate between the gate structures. A first layer of insulating material is deposited overlying the gate structures and the source/drain regions by a process of atomic layer deposition, and a second layer of insulating material is deposited overlying the first layer by a process of chemical vapor deposition. First and second openings are etched through the second layer and the first layer to expose portions of the source/drain regions. The first and second openings are filled with conductive material to form first and second spaced apart contacts, electrically isolated from each other, in electrical contact with the first and second source/drain regions.

摘要翻译： 提供了用于制造集成电路的方法，其包括形成覆盖半导体衬底的第一和第二间隔开的栅极结构，以及在栅极结构之间的半导体衬底中形成第一和第二间隔开的源/漏区。 通过原子层沉积的过程沉积覆盖栅极结构和源极/漏极区的第一绝缘材料层，并且通过化学气相沉积工艺将第二层绝缘材料沉积在第一层上。 通过第二层和第一层蚀刻第一和第二开口以暴露源/漏区的部分。 第一和第二开口用导电材料填充以形成与第一和第二源极/漏极区域电接触的彼此电隔离的第一和第二间隔开的触点。

公开(公告)号：US08492269B2

公开(公告)日：2013-07-23

申请号：US13234529

申请日：2011-09-16

申请人： Jens Heinrich ,  Ralf Richter ,  Torsten Huisinga ,  Kai Frohberg

发明人： Jens Heinrich ,  Ralf Richter ,  Torsten Huisinga ,  Kai Frohberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53257 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： In sophisticated semiconductor devices, superior contact resistivity may be accomplished for a given contact configuration by providing hybrid contact elements, at least a portion of which may be comprised of a highly conductive material, such as copper. To this end, a well-established contact material, such as tungsten, may be used as buffer material in order to preserve integrity of sensitive device areas upon depositing the highly conductive metal.

摘要翻译： 在复杂的半导体器件中，通过提供混合接触元件，对于给定的接触构型可以实现优异的接触电阻率，其中至少一部分可由高导电材料（例如铜）构成。 为此，可以使用诸如钨的良好接触材料作为缓冲材料，以便在沉积高导电性金属时保持敏感器件区域的完整性。

公开(公告)号：US08440534B2

公开(公告)日：2013-05-14

申请号：US13104474

申请日：2011-05-10

申请人： Uwe Griebenow ,  Jan Hoentschel ,  Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Frank Feustel ,  Kerstin Ruttloff

发明人： Uwe Griebenow ,  Jan Hoentschel ,  Kai Frohberg ,  Heike Berthold ,  Katrin Reiche ,  Frank Feustel ,  Kerstin Ruttloff

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/6656 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7836

摘要： Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

公开(公告)号：US08377820B2

公开(公告)日：2013-02-19

申请号：US12693030

申请日：2010-01-25

申请人： Thomas Werner ,  Kai Frohberg ,  Frank Feustel

发明人： Thomas Werner ,  Kai Frohberg ,  Frank Feustel

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a “via first/trench last” approach for forming metal lines and vias in a metallization system of a semiconductor device, a combination of two hard masks may be used, wherein the desired lateral size of the via openings may be defined on the basis of spacer elements, thereby resulting in significantly less demanding lithography conditions compared to conventional approaches.

摘要翻译： 在用于在半导体器件的金属化系统中形成金属线和通孔的通孔第一/沟槽最后方法中，可以使用两个硬掩模的组合，其中通孔开口的所需横向尺寸可以基于间隔物 因此与常规方法相比，导致光刻条件要求明显较低。

公开(公告)号：US08241973B2

公开(公告)日：2012-08-14

申请号：US12205221

申请日：2008-09-05

申请人： Uwe Griebenow ,  Kai Frohberg ,  Frank Feustel ,  Thomas Werner

发明人： Uwe Griebenow ,  Kai Frohberg ,  Frank Feustel ,  Thomas Werner

IPC分类号： H01L21/336 ,  H01L21/00

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848

摘要： The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

摘要翻译： 漏极和源极区域的厚度可以通过用适合的半导体材料重新填充空腔的腔蚀刻来减小，其中，在外延生长之前，可以进行注入工艺以便形成深的漏极和源极 对于给定的关键栅极高度，没有有助于不期望的沟道掺杂的区域。 在其他情况下，可以通过执行用于引入深漏极和源极区域的倾斜注入步骤来增强栅电极结构的有效离子阻挡长度。

公开(公告)号：US20120153405A1

公开(公告)日：2012-06-21

申请号：US13195981

申请日：2011-08-02

申请人： Jens Heinrich ,  Kai Frohberg ,  Torsten Huisinga ,  Ronny Pfuetzner

发明人： Jens Heinrich ,  Kai Frohberg ,  Torsten Huisinga ,  Ronny Pfuetzner

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L23/485 ,  H01L23/5222 ,  H01L23/53238 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： In sophisticated semiconductor devices, at least a portion of the interlayer dielectric material of the contact level may be provided in the form of a low-k dielectric material which may, in some illustrative embodiments, be accomplished on the basis of a replacement gate approach. Hence, superior electrical performance, for instance with respect to the parasitic capacitance, may be accomplished.

摘要翻译： 在复杂的半导体器件中，接触电平的层间电介质材料的至少一部分可以以低k电介质材料的形式提供，在一些说明性实施例中，可以基于替代栅极方法来实现。 因此，可以实现例如相对于寄生电容的优异的电性能。