公开(公告)号：US06387747B1

公开(公告)日：2002-05-14

申请号：US09867561

申请日：2001-05-31

申请人： Randall Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chua Chee Tee

发明人： Randall Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chua Chee Tee

IPC分类号： H01L218244

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming an RF inductor of helical shape having high Q and minimum area. The inductor is fabricated of metal or damascened linear segments formed on three levels of intermetal dielectric layers and interconnected by metal filled vias to form the complete helical shape with electrical continuity.

摘要翻译： 一种形成具有高Q值和最小面积的螺旋形RF电感器的方法。 电感器由形成在三层金属间电介质层上并由金属填充的通孔相互连接形成具有电连续性的完整螺旋形状的金属或镶嵌的线性段制成。

公开(公告)号：US06281117B1

公开(公告)日：2001-08-28

申请号：US09425994

申请日：1999-10-25

申请人： Lap Chan ,  Chaw Sing Ho ,  Fong Yau Sam Li ,  Hou Tee Ng

发明人： Lap Chan ,  Chaw Sing Ho ,  Fong Yau Sam Li ,  Hou Tee Ng

IPC分类号： H01L214763

CPC分类号： H01L21/28518 ,  Y10S977/859

摘要： A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted. Or the metal acetate layer is heat treated at localized regions using a multi-array of tips aligned in a specific layout. Or the metal acetate layer is contacted by heated metallic tips under vacuum so that the metal does not oxidize. The unreacted metal acetate layer is removed leaving the metal silicide as the uniform ultrathin silicide features.

摘要翻译： 描述了在制造集成电路中形成均匀的超薄硅化物特征的方法。 金属层沉积在硅半导体衬底的表面上。 加热的金属尖端的阵列接触金属层，由此将金属层转变为金属硅化物，在金属硅化物中金属层与金属顶端接触，并且其中不与金属尖端接触的金属层是未反应的。 除去未反应的金属层，留下金属硅化物作为均匀的超薄硅化物特征。 或者，将金属乙酸盐层旋涂在硅半导体衬底的表面上。 加热的金属尖端的阵列接触金属乙酸盐层，由此金属乙酸盐层转变为金属硅化物，其中金属尖端与金属乙酸盐层接触，并且其中未与金属尖端接触的金属乙酸盐钝化剂未反应。 或者使用在特定布局中对齐的多阵列尖端在局部区域对金属乙酸盐层进行热处理。 或者金属乙酸盐层在真空下被加热的金属尖端接触，使得金属不氧化。 除去未反应的金属乙酸盐层，留下金属硅化物作为均匀的超薄硅化物特征。

公开(公告)号：US06261935B1

公开(公告)日：2001-07-17

申请号：US09458725

申请日：1999-12-13

申请人： Alex See ,  Lap Chan ,  Ravi Sundaresan

发明人： Alex See ,  Lap Chan ,  Ravi Sundaresan

IPC分类号： H01L214763

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76895 ,  H01L29/66545 ,  H01L29/6656

摘要： A new method is provided for the creation of contact pads to the poly gate of MOS devices. STI regions are formed, layers of gate oxide, poly and SiN are deposited. The poly gate is patterned and etched leaving a layer of SiN on the surface of the gate. An oxide liner is created, an LDD implant is performed, the gate spacers are created and source/drain region implants are performed. A layer of titanium is deposited and annealed, a salicide etchback is performed to the layer of titanium creating silicided surfaces over the source and drain regions. Inter level dielectric (ILD) is deposited, the layer of ILD is polished down to the SiN layer on the top surface of the gate. The layer of SiN is removed creating a recessed gate structure. A stack of layers of titanium-amorphous silicon-titanium (Ti/Si/Ti) or a layer of WSix is deposited over the layer of ILD filling the recess on top of the gate with Ti/Si/Ti. This Ti/Si/Ti (or WSix) is patterned and etched forming a Ti/Si/Ti stack (or layer of WSix) that partially overlays the layer of ILD while also penetrating the recessed opening of the gate electrode. The layer of Ti/Si/Ti is silicided and forms the contact pad to the gate structure.

摘要翻译： 提供了一种用于向MOS器件的多晶硅栅极创建接触焊盘的新方法。 形成STI区，沉积栅氧化层，聚和SiN层。 多晶硅栅极被图案化和蚀刻，在栅极的表面上留下一层SiN层。 产生氧化物衬垫，执行LDD注入，产生栅极间隔物并执行源极/漏极区域注入。 沉积并退火一层钛，对源层和漏极区产生硅化表面的钛层进行自对准硅蚀刻蚀刻。 层间电介质（ILD）被沉积，ILD层被抛光到栅极顶表面上的SiN层。 去除SiN层，产生凹陷的栅极结构。 在TiD / Si / Ti上在栅极顶部填充凹槽的ILD层上沉积一叠钛 - 非晶硅 - 钛（Ti / Si / Ti）或一层WSix层。 该Ti / Si / Ti（或WSix）被图案化和蚀刻形成Ti / Si / Ti叠层（或WSix层），其部分覆盖ILD层，同时也穿过栅电极的凹入开口。 Ti / Si / Ti层被硅化并形成与栅极结构的接触焊盘。

公开(公告)号：US06252277B1

公开(公告)日：2001-06-26

申请号：US09392392

申请日：1999-09-09

申请人： Lap Chan ,  Cher Liang Cha ,  Eng Fong Chor ,  Gong Hao ,  Teck Koon Lee

发明人： Lap Chan ,  Cher Liang Cha ,  Eng Fong Chor ,  Gong Hao ,  Teck Koon Lee

IPC分类号： H01L2972

CPC分类号： H01L29/66621 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834

摘要： Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed. The new process, uses the same total number of photolithographic steps to form the MOSFET device elements as a conventional process but is far more protective of the thin gate oxide.

摘要翻译： 描述了形成具有嵌入在硅沟槽内的多晶硅栅电极的MOSFET。 MOSFET保留了具有光刻图案化多晶硅栅电极的常规MOSFET的所有特征，包括沿沟槽壁形成的鲁棒LDD（轻掺杂漏极）区域。 因为栅极电介质永远不会暴露于等离子体蚀刻或水性化学蚀刻，所以可以形成低于100埃的栅介质膜而没有缺陷。 在光刻图案化多晶硅栅电极的制造中遇到的过蚀刻和衬底尖峰的问题不会发生。 整个过程仅使用两个光刻步骤。 第一步骤通过图案化场隔离来定义硅有源面积，第二步限定在形成器件的有源区域内的沟槽。 新工艺使用相同的光刻步骤总数来形成MOSFET器件元件作为常规工艺，但对薄栅极氧化物的保护更为广泛。

公开(公告)号：US06251781B1

公开(公告)日：2001-06-26

申请号：US09374312

申请日：1999-08-16

申请人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

发明人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L21/76874 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating single and dual damascene copper interconnects is achieved. A semiconductor substrate layer is provided. Conductive traces are provided in an isolating dielectric layer. An intermetal dielectric layer is deposited overlying the conductive traces and the isolating dielectric layer. The intermetal dielectric layer is patterned to form trenches to expose the top surfaces of the underlying conductive traces. A barrier layer is deposited overlying the intermetal dielectric layer, the exposed conductive traces, and within the trenches. A platinum ionic seed solution is coated inside the trenches and overlying the barrier layer. A platinum seed layer is deposited from the ionic seed solution by exposing the platinum ionic seed solution to ultraviolet light. A copper layer is deposited by electroless plating to form copper interconnects, where the copper layer is only deposited overlying the platinum seed layer in the trenches, and where the deposition stops before the copper layer fills the trenches. The exposed barrier layer is polished down to the top surface of the intermetal dielectric layer. An encapsulation layer is deposited overlying the copper interconnects and the intermetal dielectric layer to complete the fabrication of the integrated circuit device.

摘要翻译： 实现了制造单和双镶嵌铜互连的方法。 提供半导体衬底层。 导电迹线设置在隔离电介质层中。 沉积覆盖导电迹线和隔离电介质层的金属间电介质层。 图案化金属间电介质层以形成沟槽以暴露下面的导电迹线的顶表面。 覆盖在金属间电介质层，暴露的导电迹线和沟槽内的阻挡层被沉积。 将铂离子种子溶液涂覆在沟槽内并覆盖阻挡层。 通过将铂离子种子溶液暴露于紫外光，从离子种子溶液沉积铂种子层。 通过无电镀沉积铜层以形成铜互连，其中铜层仅沉积在沟槽中的铂种子层上方，并且在铜层填充沟槽之前沉积停止。 暴露的阻挡层被抛光到金属间电介质层的顶表面。 沉积覆盖在铜互连和金属间电介质层上的封装层，以完成集成电路器件的制造。

公开(公告)号：US06221560B1

公开(公告)日：2001-04-24

申请号：US09373244

申请日：1999-08-12

申请人： Choi Pheng Soo ,  Lap Chan

发明人： Choi Pheng Soo ,  Lap Chan

IPC分类号： G03C500

CPC分类号： H01L21/31053 ,  Y10S148/05

摘要： A new method for planarizing silicon dioxide surfaces in semiconductor structures. Starting with a structure of an underlying layer (for instance a layer of metal lines) a layer of oxide is deposited and profiled by positive tone imaging. A layer of PPMS is deposited. Using the mask of the starting structure, the PPMS layer is exposed changing the PPMS to PPMSO in the exposed regions. The unexposed PPMS is removed, the PPMSO (unexposed regions of the PPMS) are planarized, this planarization can proceed to the point where no more PPMSO is present (the PPMSO “columns” are removed together with the intra-layer of patterned oxide). The surface thus created shows excellent planarity, this surface can be further planarized down to the top level of the underlying pattern, if it is desirable to do so.

摘要翻译： 一种在半导体结构中平坦化二氧化硅表面的新方法。 从底层（例如一层金属线）的结构开始，通过正色成像沉积和分析氧化层。 存放一层PPMS。 使用起始结构的掩模，PPMS层暴露在暴露区域中将PPMS改变为PPMSO。 去除未曝光的PPMS，PPMSO（PPMS的未曝光区域）被平坦化，该平面化可以进行到不再存在PPMSO的点（与图案化氧化物层内的PPMSO“列”一起被去除）。 如此创建的表面显示出优异的平面度，如果希望这样做，则该表面可以进一步平坦化到底层图案的顶层。

公开(公告)号：US06214728B1

公开(公告)日：2001-04-10

申请号：US09196604

申请日：1998-11-20

申请人： Lap Chan ,  Sam Fong Yau Li ,  Hou Tee Ng

发明人： Lap Chan ,  Sam Fong Yau Li ,  Hou Tee Ng

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug. The surface of the encapsulating metal deposit is formed by overgrowth above the plug hole followed by polishing the surface of the insulator layer removing the overgrowth of the metal layer polished by a CMP process to planarize the surface of the insulator layer which is the top surface of device to achieve coplanarity of metal layer with the topography of the insulator layer.

摘要翻译： 掺杂硅半导体衬底上的封装铜插头具有覆盖有绝缘体的衬底表面，其上形成有扩散阻挡层的插塞孔，孔形成在孔的顶部和顶部。 塞孔部分地填充有无电沉积的铜金属塞。 封装金属沉积物覆盖插塞，而不会发生任何中间氧化和降解。 在从铜到铜的共沉积物的转变中，封装的Pt，Pd和/或Ag金属在无电镀浴中沉积而不氧化和降解，然后纯化沉积包封金属层以堵住塞子。 封装金属沉积物的表面通过在插塞孔上方过度生长而形成，随后抛光绝缘体层的表面，从而去除通过CMP工艺抛光的金属层的过度生长，以使作为顶部表面的绝缘体层的表面平坦化 器件实现金属层与绝缘体层的形貌的共面性。

公开(公告)号：US06204137B1

公开(公告)日：2001-03-20

申请号：US09556386

申请日：2000-04-24

申请人： Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

发明人： Kok Hin Teo ,  Feng Chen ,  Alex See ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/76224

摘要： A new method of forming MOS transistors has been achieved. A pad oxide layer is grown. A silicon nitride layer is deposited. Trenches are etched for planned STI. A trench liner is grown inside of the trenches. A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to complete the STI. The same silicon nitride layer is patterned to form dummy gates. A gate liner layer is deposited. Ions are implanted to form lightly doped drain junctions. Sidewall spacers are formed adjacent to the dummy gate electrodes and the shallow trench isolations. Ions are implanted to form the drain and source junctions. An epitaxial silicon layer is grown overlying the source and drain junctions. A metal layer is deposited. The epitaxial silicon layer is converted into sulicide to form silicided source and drain contacts. An interlevel dielectric layer is deposited and polished down to the dummy gates. The dummy gates are etched away to form openings for the planned transistor gates. A gate oxide layer is deposited lining the transistor gate openings. A gate electrode layer is deposited to fill the transistor gate openings. The gate electrode layer is patterned to complete the transistor gates.

摘要翻译： 已经实现了形成MOS晶体管的新方法。 生长衬垫氧化物层。 沉积氮化硅层。 沟槽蚀刻为计划的STI。 在沟槽内生长沟槽衬垫。 沉积填充沟槽的沟槽氧化物层。 将沟槽氧化物层抛光以完成STI。 将相同的氮化硅层图案化以形成伪栅极。 沉积栅极衬垫层。 植入离子以形成轻掺杂的漏极结。 侧壁间隔件形成在与虚拟栅极电极和浅沟槽隔离件相邻处。 植入离子以形成漏极和源极结。 生长在源极和漏极结上方的外延硅层。 沉积金属层。 将外延硅层转化为硅化物以形成硅化源极和漏极触点。 将层间电介质层沉积并抛光到虚拟栅极。 蚀刻掉虚拟栅极以形成预定晶体管栅极的开口。 在晶体管栅极开口上沉积栅极氧化物层。 沉积栅极电极层以填充晶体管栅极开口。 图案化栅极电极层以完成晶体管栅极。

公开(公告)号：US6121130A

公开(公告)日：2000-09-19

申请号：US192338

申请日：1998-11-16

申请人： Chee Tee Chua ,  Yuan-Ping Lee ,  Mei Sheng Zhou ,  Lap Chan

发明人： Chee Tee Chua ,  Yuan-Ping Lee ,  Mei Sheng Zhou ,  Lap Chan

IPC分类号： H01L21/268 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L21/469

CPC分类号： H01L21/76825 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/268 ,  H01L21/31058 ,  H01L21/3122 ,  H01L21/76801 ,  H01L21/76834

摘要： A process for curing low-k spin-on dielectric layers based on alkyl silsesquioxane polymers by laser scanning is described wherein curing is achieved by both photothermal and photochemical mechanisms. The layers are deposited by spin deposition, dried and cured by raster scanning with a pulsed laser at energies between 0.1 and 1 Joules/cm.sup.2. Because the laser causes heating of the layer, a nitrogen jet is applied in the wake of the scanning laser beam to rapidly cool the layer and to inhibit oxidation and moisture absorption. The laser induced heating also assists in the discharge of moisture and by-products of the polymerization process. The laser operates at wavelengths between 200 and 400 nm. Insulative layers such as silicon oxide are sufficiently transparent at these so that oxide segments overlying the polymer layer do not inhibit the curing process. Implementation of the laser scanning feature is readily incorporated into an existing spin-on deposition and curing tool.

摘要翻译： 描述了通过激光扫描固化基于烷基倍半硅氧烷聚合物的低k自旋电介质层的方法，其中通过光热和光化学机理实现固化。 通过旋转沉积沉积这些层，通过用0.1至1焦耳/ cm2的能量的脉冲激光进行光栅扫描来干燥和固化。 因为激光引起层的加热，所以在扫描激光束之后施加氮气喷射以快速冷却层并抑制氧化和吸湿。 激光诱导加热还有助于排出水分和聚合过程的副产物。 激光器工作在200和400 nm之间的波长。 绝缘层例如氧化硅在这些处是足够透明的，使得覆盖聚合物层的氧化物段不会阻碍固化过程。 激光扫描特征的实现容易地并入现有的旋涂沉积和固化工具中。

公开(公告)号：US6103594A

公开(公告)日：2000-08-15

申请号：US392393

申请日：1999-09-09

申请人： Alex See ,  Lap Chan

发明人： Alex See ,  Lap Chan

IPC分类号： H01L21/762 ,  H01L21/761

CPC分类号： H01L21/76229

摘要： A method of forming shallow trench isolations is achieved. STI structures so formed do not exhibit isolation oxide thinning due to dishing and erosion problems during the oxide CMP process. A silicon substrate is provided. A first dielectric layer is formed overlying the silicon substrate. A silicon nitride layer is deposited. The silicon nitride layer, the first dielectric layer, and the silicon substrate are etched to form trenches for planned shallow trench isolations. A second dielectric layer is deposited overlying the silicon nitride layer and the trenches. The second dielectric layer is etched to form sidewall spacers inside the trenches. A silicon layer is selectively grown overlying the silicon substrate only where the silicon substrate is exposed in the trenches, and wherein the step of growing is stopped before the silicon layer exceeds the top surface of the silicon nitride layer. A third dielectric layer is deposited overlying the silicon nitride layer, the sidewall spacers, and the silicon layer. The third dielectric layer is polished down to the top surface of the silicon nitride layer to complete the shallow trench isolations where the silicon nitride layer acts as a polishing stop, and the integrated circuit device is completed.

摘要翻译： 实现形成浅沟槽隔离的方法。 如此形成的STI结构在氧化物CMP工艺期间由于凹陷和侵蚀问题而不表现出隔离氧化物变薄。 提供硅衬底。 在硅衬底上形成第一介电层。 沉积氮化硅层。 蚀刻氮化硅层，第一介电层和硅衬底以形成用于规划的浅沟槽隔离的沟槽。 第二介质层沉积在氮化硅层和沟槽之上。 蚀刻第二电介质层以在沟槽内形成侧壁间隔物。 只有在硅衬底暴露在沟槽中的硅衬底上选择性地生长硅层，并且其中在硅层超过氮化硅层的顶表面之前停止生长步骤。 第三电介质层沉积在氮化硅层，侧壁间隔物和硅层上。 第三电介质层被抛光到氮化硅层的顶表面，以完成浅沟槽隔离，其中氮化硅层用作抛光停止，并且集成电路器件完成。