公开(公告)号：US06803330B2

公开(公告)日：2004-10-12

申请号：US09975256

申请日：2001-10-12

申请人： Krishnaswamy Ramkumar ,  Sundar Narayanan

发明人： Krishnaswamy Ramkumar ,  Sundar Narayanan

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/518

摘要： A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas is disclosed. The nitridation process can be carried out at lower temperatures and pressures than a conventional nitrous oxide anneal while still achieving acceptable levels of nitridation. The nitridation process can be conducted at atmospheric or sub-atmospheric pressures. As a result, the nitridation process can be used to form nitrided gate oxide layers in-situ in a CVD furnace. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

摘要翻译： 公开了通过用一氧化氮（NO）气体退火预形成的氧化物层来对栅极氧化物层进行氮化的方法。 氮化过程可以在比常规氧化亚氮退火更低的温度和压力下进行，同时仍然达到可接受的氮化水平。 氮化过程可以在大气压或低于大气压的压力下进行。 结果，可以使用氮化工艺在CVD炉中原位形成氮化的栅极氧化物层。 氮化栅氧化层可以在氮化步骤后的第二氧化步骤中任选地再氧化。 然后可以在氮化栅极氧化物层的顶部上或在再氧化和氮化的栅极氧化物层的顶部上沉积栅极电极层（例如，硼掺杂的多晶硅）。

公开(公告)号：US06777307B1

公开(公告)日：2004-08-17

申请号：US10010833

申请日：2001-12-04

申请人： Krishnaswamy Ramkumar ,  Steven S. Hedayati

发明人： Krishnaswamy Ramkumar ,  Steven S. Hedayati

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/3081 ,  H01L21/31053

摘要： A method is provided which includes planarizing structures and/or layers such that step heights of reduced and more uniform thicknesses may be formed. In particular, a method is provided which includes polishing an upper layer of a topography to expose a first underlying layer and etching away remaining portions of the first underlying layer to expose a second underlying layer. The topography may then be subsequently planarized. As such, a method for fabricating shallow trench isolation regions may include forming one or more trenches extending through a stack arranged over a semiconductor substrate. Such a method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack.

摘要翻译： 提供了一种包括平坦化结构和/或层的方法，使得可以形成减小和更均匀厚度的台阶高度。 特别地，提供了一种方法，其包括抛光地形的上层以暴露第一下层并蚀刻掉第一下层的剩余部分以暴露第二下层。 随后可以将形貌平面化。 因此，用于制造浅沟槽隔离区域的方法可以包括形成延伸穿过布置在半导体衬底上的堆叠的一个或多个沟槽。 这种方法还可以包括在沟槽和层叠层上覆盖电介质，使得沟槽被电介质填充。 然后电介质可以被平坦化，使得保留在沟槽内的电介质的上表面与堆叠的相邻层的上表面共面。

公开(公告)号：US06664120B1

公开(公告)日：2003-12-16

申请号：US10023065

申请日：2001-12-17

申请人： Sundar Narayanan ,  Krishnaswamy Ramkumar

发明人： Sundar Narayanan ,  Krishnaswamy Ramkumar

IPC分类号： H01L2166

CPC分类号： H01L22/20 ,  G01N1/32 ,  G01N19/06 ,  H01L22/34

摘要： A method and a structure are provided for measuring a concentration of an impurity within a layer arranged upon a semiconductor substrate. The method may include exposing the layer and semiconductor substrate to oxidizing conditions and determining a difference in total dielectric thickness above the substrate from before to after exposing the layer and substrate. The difference may be correlated to a concentration of the impurity. In some cases, the method may include designating a plurality of measurement locations on the layer such that a concentration profile of the impurity within the layer may be determined. In some embodiments, exposing the layer and substrate may include forming an oxidized interface between the layer and the semiconductor substrate. Preferably, the oxidized interface is thicker underneath portions of the layer with a lower concentration of the impurity than underneath portions of the layer with a higher concentration of the impurity.

摘要翻译： 提供了一种测量布置在半导体衬底上的层内的杂质浓度的方法和结构。 该方法可以包括将层和半导体衬底暴露于氧化条件，并确定在暴露层和衬底之前至之后的衬底上的总电介质厚度的差异。 该差异可能与杂质的浓度相关。 在一些情况下，该方法可以包括指定层上的多个测量位置，使得可以确定该层内的杂质的浓度分布。 在一些实施例中，暴露层和衬底可以包括在层和半导体衬底之间形成氧化界面。 优选地，具有较低浓度的杂质的层的下部的氧化界面比具有较高浓度杂质的层的下部更厚。

公开(公告)号：US06436799B1

公开(公告)日：2002-08-20

申请号：US09670089

申请日：2000-09-26

申请人： Krishnaswamy Ramkumar ,  Manuj Rathor

发明人： Krishnaswamy Ramkumar ,  Manuj Rathor

IPC分类号： H01L21425

CPC分类号： H01L29/518 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/517

摘要： A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

公开(公告)号：US06399462B1

公开(公告)日：2002-06-04

申请号：US08885046

申请日：1997-06-30

申请人： Krishnaswamy Ramkumar ,  Sang S. Kim ,  Sharmin Sadoughi ,  Pamela Trammel ,  Avner Shelem

发明人： Krishnaswamy Ramkumar ,  Sang S. Kim ,  Sharmin Sadoughi ,  Pamela Trammel ,  Avner Shelem

IPC分类号： H01L2176

CPC分类号： H01L21/7621

摘要： A method of forming a field oxide or isolation region in a semiconductor die. A nitride layer (over an oxide layer disposed over a substrate) is patterned and subsequently etched so that the nitride layer has a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the nearly vertical sidewall of the nitride layer. A field oxide is then grown in the recess using a high pressure, dry oxidizing atmosphere. The sloped sidewall of the substrate effectively moves the face of the exposed substrate away from the edge of the nitride layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and a nearly non-existent bird's beak. The desirable range of slopes for the substrate sidewall is approximately 50°-80° with respect to a nearly planar surface of the substrate in the recess.

摘要翻译： 一种在半导体管芯中形成场氧化物或隔离区域的方法。 对氮化物层（在衬底上方的氧化物层上方）进行构图并随后进行蚀刻，使得氮化物层具有几乎垂直的侧壁。 蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氮化物层的几乎垂直侧壁具有倾斜表面的凹部。 然后使用高压，干燥的氧化气氛将场氧化物生长在凹陷中。 衬底的倾斜侧壁有效地将暴露的衬底的表面远离氮化物层侧壁的边缘移动。 与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。 这导致氧化物侵蚀的减少和几乎不存在的鸟的喙。 相对于凹部中的基板的几乎平坦的表面，衬底侧壁的期望的斜率范围大约为50°-80°。

公开(公告)号：US08283261B2

公开(公告)日：2012-10-09

申请号：US12124855

申请日：2008-05-21

申请人： Krishnaswamy Ramkumar

发明人： Krishnaswamy Ramkumar

IPC分类号： H01L21/31

CPC分类号： H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833

摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.

摘要翻译： 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括提供其上设置有电荷捕获层的衬底。 然后通过将电荷捕获层暴露于自由基氧化过程，电荷俘获层的一部分被氧化以形成电荷俘获层上方的阻挡电介质层。

公开(公告)号：US08222688B1

公开(公告)日：2012-07-17

申请号：US12767105

申请日：2010-04-26

申请人： Fredrick Jenne ,  Krishnaswamy Ramkumar

发明人： Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  G11C16/04 ,  H01L21/022 ,  H01L21/02323 ,  H01L27/11563 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

摘要： A semiconductor device includes a substrate, a first oxide layer formed on the substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.

摘要翻译： 半导体器件包括衬底，形成在衬底上的第一氧化物层，形成在第一氧化物层上的富氧氮化物层，形成在富氧氮化物层上的第二氧化物层和形成的不透氧氮化物层 在第二氧化物层上。

公开(公告)号：US08119538B1

公开(公告)日：2012-02-21

申请号：US11836683

申请日：2007-08-09

申请人： Jeong Soo Byun ,  Krishnaswamy Ramkumar

发明人： Jeong Soo Byun ,  Krishnaswamy Ramkumar

IPC分类号： H01L21/31

CPC分类号： H01L21/28282 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02323 ,  H01L21/02326

摘要： A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.

摘要翻译： 提供制造半导体结构的方法。 该方法包括使用高密度等离子体氧化工艺形成介电层。 电介质层在存储层上，并且在高密度等离子体氧化过程中存储层的厚度减小。

公开(公告)号：US08071453B1

公开(公告)日：2011-12-06

申请号：US12608886

申请日：2009-10-29

申请人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

发明人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

IPC分类号： H01L21/336

CPC分类号： H01L21/768 ,  H01L27/11568 ,  H01L29/792

摘要： A method of ONO integration of a non-volatile memory device (e.g. EEPROM, floating gate FLASH and SONOS) into a baseline MOS device (e.g. MOSFET) is described. In an embodiment the bottom two ONO layers are formed prior to forming the channel implants into the MOS device, and the top ONO layer is formed simultaneously with the gate oxide of the MOS device.

摘要翻译： 描述了将非易失性存储器件（例如EEPROM，浮动栅极FLASH和SONOS）的ONO集成到基准MOS器件（例如MOSFET）中的方法。 在一个实施例中，在将沟道植入物形成MOS器件之前形成底部的两个ONO层，并且顶部ONO层与MOS器件的栅极氧化物同时形成。

公开(公告)号：US20080293255A1

公开(公告)日：2008-11-27

申请号：US12124855

申请日：2008-05-21

申请人： Krishnaswamy Ramkumar

发明人： Krishnaswamy Ramkumar

IPC分类号： H01L21/31

CPC分类号： H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833

摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking Dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.

摘要翻译： 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括提供其上设置有电荷捕获层的衬底。 然后通过将电荷捕获层暴露于自由基氧化过程，电荷俘获层的一部分被氧化以形成电荷俘获层上方的阻挡介电层。