公开(公告)号：US11462629B2

公开(公告)日：2022-10-04

申请号：US16519225

申请日：2019-07-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: H01L27/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/112

Abstract: Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

公开(公告)号：US20220277777A1

公开(公告)日：2022-09-01

申请号：US17693871

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11529 ,  G11C16/26 ,  G11C5/02 ,  G11C7/12 ,  G11C7/22

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US11282556B2

公开(公告)日：2022-03-22

申请号：US16983604

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C8/10 ,  G11C7/02 ,  G11C8/12 ,  G11C8/16 ,  G11C8/18 ,  G11C5/02 ,  G11C5/06 ,  G11C11/408 ,  G11C7/00 ,  G11C13/00

Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

公开(公告)号：US20220028891A1

公开(公告)日：2022-01-27

申请号：US17498503

申请日：2021-10-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

公开(公告)号：US11182074B2

公开(公告)日：2021-11-23

申请号：US16401089

申请日：2019-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G11C16/26 ,  G11C16/30 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C13/00 ,  G11C16/04

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US20210249089A1

公开(公告)日：2021-08-12

申请号：US17245275

申请日：2021-04-30

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/10 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

公开(公告)号：US20210216217A1

公开(公告)日：2021-07-15

申请号：US17157272

申请日：2021-01-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/00 ,  H01L29/51 ,  H01L27/1159 ,  H01L27/11597

Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

公开(公告)号：US10916313B2

公开(公告)日：2021-02-09

申请号：US16574585

申请日：2019-09-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  H01L27/115

Abstract: Apparatus configured to establish a negative potential in a body of a memory cell during an access operation of another memory cell, and methods of operating such an apparatus, as well as apparatus configured to establish a negative potential in a body of a memory cell in response to a timer, or before a sensing operation of the memory cell.

公开(公告)号：US10901623B2

公开(公告)日：2021-01-26

申请号：US16727441

申请日：2019-12-26

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/00 ,  H01L29/51 ,  H01L27/1159 ,  H01L27/11597

Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

公开(公告)号：US10354030B2

公开(公告)日：2019-07-16

申请号：US16105571

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F17/50 ,  G11C7/22 ,  G11C29/02 ,  G11C7/10 ,  G11C13/00

Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.