公开(公告)号：US20190258404A1

公开(公告)日：2019-08-22

申请号：US16401089

申请日：2019-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US09910594B2

公开(公告)日：2018-03-06

申请号：US14933874

申请日：2015-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/42

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US11698725B2

公开(公告)日：2023-07-11

申请号：US17452468

申请日：2021-10-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G11C16/26 ,  G11C16/30 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C13/00 ,  G11C16/04

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/42 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0038 ,  G11C16/0483 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US20220155958A1

公开(公告)日：2022-05-19

申请号：US17452468

申请日：2021-10-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G11C16/26 ,  G11C16/30 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US20180217782A1

公开(公告)日：2018-08-02

申请号：US15940351

申请日：2018-03-29

Applicant: Micron Technology, Inc.

Inventor： Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G06F3/06 ,  G11C16/10

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0679 ,  G11C7/1084 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/32

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.

公开(公告)号：US20180143784A1

公开(公告)日：2018-05-24

申请号：US15359306

申请日：2016-11-22

Applicant: Micron Technology, Inc.

Inventor： Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G06F3/06 ,  G11C16/10

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0679 ,  G11C7/1084 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/32

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.

公开(公告)号：US20180136845A1

公开(公告)日：2018-05-17

申请号：US15854622

申请日：2017-12-26

Applicant: Micron Technology, Inc.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/42 ,  G11C8/12 ,  G11C11/5642 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US11182074B2

公开(公告)日：2021-11-23

申请号：US16401089

申请日：2019-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G11C16/26 ,  G11C16/30 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C13/00 ,  G11C16/04

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US09977622B1

公开(公告)日：2018-05-22

申请号：US15359306

申请日：2016-11-22

Applicant: Micron Technology, Inc.

Inventor： Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/10

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0679 ,  G11C7/1084 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/32

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. One example method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.

公开(公告)号：US10430114B2

公开(公告)日：2019-10-01

申请号：US15940351

申请日：2018-03-29

Applicant: Micron Technology, Inc.

Inventor： Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/10 ,  G11C7/10 ,  G11C11/56 ,  G11C16/32

Abstract: Apparatuses and methods for performing buffer operations in memory are provided. A method can include storing second page data and third page data on a buffer while programming first page data during a first pass programming operation and programming the second page data and the third page data from the buffer to the array of memory cells during a second pass programming operation.