公开(公告)号：US20230393789A1

公开(公告)日：2023-12-07

申请号：US17831263

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0622 ,  G06F3/0679

Abstract: Some memory dice in a stack can be connected externally to the stack and other memory dice in the stack can be connected internally to the stack. The memory dice that are connected externally can act as interface dice for other memory dice that are connected internally thereto. Data protection and recovery schemes provided for the stacks of memory dice can be based on data that are transferred in a single data stream without a discontinuity between those data transfers from the memory dice of the stacks.

公开(公告)号：US11830548B2

公开(公告)日：2023-11-28

申请号：US17707116

申请日：2022-03-29

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin

IPC: G11C8/00 ,  G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, and a logic circuit portion operatively coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan memory addresses of the memory device, and to generate seasoning pulses to be applied to the addressed pages of the memory device. A related electronic system and related methods are also disclosed.

公开(公告)号：US11804271B2

公开(公告)日：2023-10-31

申请号：US17726351

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Umberto Di Vincenzo ,  Daniele Balluchi

IPC: G11C11/00 ,  G11C16/30 ,  G11C16/04

CPC classification number: G11C16/30 ,  G11C16/0483

Abstract: Methods, systems, and devices for operational modes for reduced power consumption in a memory system are described. A memory device may be coupled with a capacitor of a power management integrated circuit (PMIC). The memory device may operate in a first mode where a supply voltage is provided to the memory device from the PMIC. The memory device may operate in a second mode where it is isolated from the PMIC. When isolated, a node of the memory device (e.g., an internal node) may be discharged while the capacitor of the PMIC remains charged. When the memory device resumes operating in the first mode, a supply voltage may be provided to it based on the residual charge of the capacitor.

公开(公告)号：US11769566B2

公开(公告)日：2023-09-26

申请号：US17366988

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin

IPC: G11C29/42 ,  G11C29/18 ,  G11C16/26 ,  H03K19/21 ,  G11C16/10

CPC classification number: G11C29/42 ,  G11C16/102 ,  G11C16/26 ,  G11C29/18 ,  H03K19/21 ,  G11C2029/1802

Abstract: The present disclosure includes apparatuses, methods, and systems for programming codewords for error correction operations to memory. An embodiment includes a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells, and circuitry configured to program a portion of a codeword for an error correction operation to one of the plurality of groups of memory cells by determining an address in that group of memory cells by performing an XOR operation on an address of one of the plurality of sub-groups of that group of memory cells, and programming the portion of the codeword to the determined address.

公开(公告)号：US11574669B2

公开(公告)日：2023-02-07

申请号：US17502451

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato

IPC: G11C11/4074 ,  G06F12/14 ,  G11C11/409

Abstract: Methods, systems, and devices for distribution-following access operations for a memory device are described. In an example, the described techniques may include identifying an activation of a first memory cell at a first condition of a biasing operation, and identifying an activation of a second memory cell at a second condition of the biasing operation, and determining a parameter of an access operation based at least in part on a difference between the first condition and the second condition. In some examples, the memory cells may be associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time.

公开(公告)号：US20220415426A1

公开(公告)日：2022-12-29

申请号：US17361419

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Christophe Vincent Antoine Laurent

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/56

Abstract: Methods, systems, and devices for shared error correction coding (ECC) circuitry are described. For example, a memory device configured with shared ECC circuitry may be configured to receive data at the shared circuitry from either a host device or a set of memory cells of the memory device. The shared circuitry may be configured to generate a set of multiple syndromes associated with a cyclic error correction code, based on the received data. As part of an encoding process, an encoder circuit may generate a set of parity bits based on the generated syndromes. As part of a decoding process, a decoder circuit may generate an error vector for decoding the received data, based on the generated syndromes. The decoder circuit may also correct one or more errors in the received data based on generating the error vector.

公开(公告)号：US20220382630A1

公开(公告)日：2022-12-01

申请号：US17752538

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Daniele Balluchi

IPC: G06F11/10 ,  G06F11/07

Abstract: Systems, apparatuses, and methods related to memory bank protection are described. A quantity of errors within a single memory bank can be determined and the determined quantity can be used to further determine whether to access other memory banks to correct the determined quantity. The memory bank protection described herein can avoid a single memory bank of a memory die being a single point of failure (SPOF).

公开(公告)号：US20220253237A1

公开(公告)日：2022-08-11

申请号：US17677586

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Marco Sforzin ,  Paolo Amato

IPC: G06F3/06

Abstract: Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

公开(公告)号：US20220100244A1

公开(公告)日：2022-03-31

申请号：US17033583

申请日：2020-09-25

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Ferdinando Bedeschi ,  Daniele Balluchi

IPC: G06F1/26

Abstract: Methods, systems, and devices for a memory system with centralized power management are described. A memory system may include memory devices and a power management circuit. The memory devices may use one or more supply voltages during operation of the memory devices, which may include supply voltages received from an external device and high supply voltages generated within the memory system. The power management circuit may receive supply voltages from the external device and generate the supply voltages to the memory devices. The memory devices may exclude charge pump circuitry for generating supply voltages and may instead include pads for receiving the supply voltages from the power management circuit, in some examples. The memory system may include a controller that is configured to determine an amount of power to provide to the memory devices and transmit an indication of the amount of power to the power management circuit.

公开(公告)号：US20220036937A1

公开(公告)日：2022-02-03

申请号：US17502451

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato

IPC: G11C11/4074 ,  G06F12/14 ,  G11C11/409

Abstract: Methods, systems, and devices for distribution-following access operations for a memory device are described. In an example, the described techniques may include identifying an activation of a first memory cell at a first condition of a biasing operation, and identifying an activation of a second memory cell at a second condition of the biasing operation, and determining a parameter of an access operation based at least in part on a difference between the first condition and the second condition. In some examples, the memory cells may be associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time.