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    APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY
    91.
    发明申请
    APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY 有权
    使用感应电路进行奇偶校验的装置和方法

    公开(公告)号：US20150357007A1

    公开(公告)日：2015-12-10

    申请号：US14713724

    申请日：2015-05-15

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning ,  Richard C. Murphy

    IPC: G11C7/06 ,  G11C7/22 ,  G06F11/10 ,  G11C7/10

    CPC classification number: G11C7/06 ,  G06F11/10 ,  G06F11/1048 ,  G11C7/10 ,  G11C7/22 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/4091

    Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.

    Abstract translation: 本公开包括与使用感测电路的奇偶校验相关的装置和方法。 示例性方法可以包括：通过确定与数据数量对应的奇偶校验值来保护，使用感测电路存储在耦合到阵列的感测线的相应数量的存储单元中的数量值，而不从阵列传送数据 通过输入/输出线。 例如，奇偶校验值可以由多个异或运算确定。 该方法可以包括将奇偶校验值存储在耦合到感测线的另一个存储单元中。

    Independently addressable memory array address spaces
    93.
    发明授权
    Independently addressable memory array address spaces 有权
    独立可寻址的存储器阵列地址空间

    公开(公告)号：US09153305B2

    公开(公告)日：2015-10-06

    申请号：US14015732

    申请日：2013-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning

    IPC: G11C8/00 ,  G11C8/10

    CPC classification number: G11C8/10 ,  G06F9/30 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/0888 ,  G06F13/40 ,  G06F2212/7202 ,  G11C7/06 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/419 ,  G11C15/04 ,  G11C2207/2245 ,  Y02D10/13

    Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

    Abstract translation: 本公开的示例提供用于访问存储器阵列地址空间的设备和方法。 一种示例性存储器阵列，其包括第一地址空间，该第一地址空间包括耦合到第一数量的选择线和多条感测线的存储器单元，以及包括耦合到第二数量的选择线的存储器单元和感测线的数量的第二地址空间 。 第一地址空间相对于第二地址空间可独立地寻址。

    MEMORY MAPPING
    94.
    发明申请
    MEMORY MAPPING 审中-公开
    记忆映射

    公开(公告)号：US20150270015A1

    公开(公告)日：2015-09-24

    申请号：US14219639

    申请日：2014-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Richard C. Murphy ,  Troy A. Manning

    IPC: G11C29/18 ,  G11C29/44

    CPC classification number: G11C29/18 ,  G11C29/44 ,  G11C2029/1806 ,  G11C2029/4402

    Abstract: The present disclosure includes apparatuses, electronic device readable media, and methods for memory mapping. One example method can include testing a memory identifier against an indication corresponding to a set of mapped memory identifiers, and determining a memory location corresponding to the memory identifier responsive to testing.

    Abstract translation: 本公开包括设备，电子设备可读介质和用于存储器映射的方法。 一个示例性方法可以包括针对与映射的存储器标识符的集合相对应的指示来测试存储器标识符，以及响应于测试来确定与存储器标识符相对应的存储器位置。

    APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
    95.
    发明申请
    APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY 有权
    使用感应电路执行逻辑操作的装置和方法

    公开(公告)号：US20150138896A1

    公开(公告)日：2015-05-21

    申请号：US14538399

    申请日：2014-11-11

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning

    IPC: G11C7/10 ,  G11C7/06

    CPC classification number: G11C7/22 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/068 ,  G06F7/523 ,  G06F12/00 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1087 ,  G11C11/4074 ,  G11C11/4091 ,  H03K19/0013 ,  H03K19/1776

    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

    Abstract translation: 本公开包括与使用感测电路执行逻辑运算相关的装置和方法。 示例性设备包括存储器单元阵列和感测电路，该电路包括耦合到该阵列的感测线的主锁存器。 感测电路可以被配置为通过感测耦合到感测线的存储器单元来执行逻辑操作的第一操作阶段，通过感测耦合到所述逻辑操作的相应数量的不同存储器单元执行逻辑操作的多个中间操作阶段 并且在不执行感测线地址访问的情况下，累积第一操作阶段的结果和耦合到主锁存器的次锁存器中的中间操作相位的数量。

    Memory address translation
    98.
    发明授权
    Memory address translation 有权

    公开(公告)号：US08756400B2

    公开(公告)日：2014-06-17

    申请号：US13859502

    申请日：2013-04-09

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning ,  Martin L. Culley ,  Troy D. Larsen

    IPC: G06F12/00

    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

    Modifiable repair solutions for a memory array
    100.
    发明授权
    Modifiable repair solutions for a memory array 有权

    公开(公告)号：US11430539B2

    公开(公告)日：2022-08-30

    申请号：US16914927

    申请日：2020-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning ,  Troy D. Larsen ,  Jonathan D. Harms ,  Glen E. Hush ,  Timothy P. Finkbeiner

    IPC: G11C29/44 ,  G11C29/42 ,  G11C29/00 ,  G11C29/18 ,  G11C29/24

    Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.

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