公开(公告)号：US06214731B1

公开(公告)日：2001-04-10

申请号：US09442771

申请日：1999-11-18

申请人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

发明人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.

摘要翻译： 具有改善的电迁移电阻的Cu互连图案通过沉积阻挡金属层（例如W或WN）来形成，以对电介质层中的开口进行排列。 沉积的阻挡金属层的暴露表面用硅烷或二氯苯胺处理以在其上形成薄硅层。 然后沉积Cu以填充开口并与薄硅层反应以在Cu和阻挡金属层之间的界面处形成Cu硅化物的薄层，从而降低界面缺陷密度并提高电迁移阻力。

公开(公告)号：US06190966B1

公开(公告)日：2001-02-20

申请号：US08823953

申请日：1997-03-25

申请人： Minh Van Ngo ,  Sunil Mehta

发明人： Minh Van Ngo ,  Sunil Mehta

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  Y10S438/97

摘要： A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480° C. such that the etch stop layer has a very low concentration of hydrogen ions. The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.

公开(公告)号：US6165894A

公开(公告)日：2000-12-26

申请号：US131872

申请日：1998-08-10

申请人： Shekhar Pramanick ,  Takeshi Nogami ,  Minh Van Ngo

发明人： Shekhar Pramanick ,  Takeshi Nogami ,  Minh Van Ngo

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/76886 ,  H01L21/76834 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with an ammonia plasma followed by depositing the diffusion barrier layer on the treated surface. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu/Cu alloy interconnect with an ammonia plasma, and depositing a silicon nitride diffusion barrier layer directly on the plasma treated surface.

摘要翻译： 通过用氨等离子体处理Cu或Cu合金互连构件的暴露表面，然后在经处理的表面上沉积扩散阻挡层，扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附性显着增强。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，用氨等离子体处理Cu / Cu合金互连的暴露表面，并直接沉积氮化硅扩散阻挡层 在等离子体处理的表面上。

公开(公告)号：US6096662A

公开(公告)日：2000-08-01

申请号：US824748

申请日：1997-03-26

申请人： Minh Van Ngo ,  Darin Arthur Chan

发明人： Minh Van Ngo ,  Darin Arthur Chan

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of manufacturing a semiconductor device with improved adhesion between the local interconnect etch stop layer and the thermal oxide in an isolation region. The thermal oxide is treated with an NH.sub.3 /N.sub.2 plasma. The local interconnect etch stop layer is either silicon nitride or silicon oxynitride. A layer of a dielectric material such as PECVD SiO.sub.2 is formed on the local interconnect etch stop layer.

摘要翻译： 一种制造半导体器件的方法，该半导体器件具有改善局部互连蚀刻停止层和隔离区域中的热氧化物之间的粘合性。 热氧化物用NH 3 / N 2等离子体处理。 局部互连蚀刻停止层是氮化硅或氮氧化硅。 在局部互连蚀刻停止层上形成诸如PECVD SiO 2的电介质材料层。

公开(公告)号：US6093973A

公开(公告)日：2000-07-25

申请号：US163601

申请日：1998-09-30

申请人： Minh Van Ngo ,  Bhanwar Singh ,  Dawn Hopper ,  Carmen Morales

发明人： Minh Van Ngo ,  Bhanwar Singh ,  Dawn Hopper ,  Carmen Morales

IPC分类号： G03F7/09 ,  G03F7/11 ,  H01L23/544

CPC分类号： G03F7/091 ,  G03F7/11 ,  Y10S257/915

摘要： An oxide hard mask is formed between a deep ultraviolet photoresist and an anti-reflective coating to prevent interactions with the photoresist, thereby preventing reduction of a critical dimension of a patterned conductive layer. Embodiments include depositing a substantially nitrogen free oxide layer on the anti-reflective coating, such as a silicon oxide derived from tertaethyl orthosilicate by plasma enhanced chemical vapor deposition.

摘要翻译： 在深紫外光致抗蚀剂和抗反射涂层之间形成氧化物硬掩模以防止与光致抗蚀剂的相互作用，从而防止图案化导电层的临界尺寸的降低。 实施方案包括在抗反射涂层上沉积基本上无氮的氧化物层，例如通过等离子体增强化学气相沉积衍生自原硅酸三乙酯的氧化硅。

公开(公告)号：US6060393A

公开(公告)日：2000-05-09

申请号：US993888

申请日：1997-12-18

申请人： Minh Van Ngo ,  Darin A. Chan ,  David K. Foote

发明人： Minh Van Ngo ,  Darin A. Chan ,  David K. Foote

IPC分类号： H01L21/768 ,  H01L21/304

CPC分类号： H01L21/76895 ,  H01L21/76801

摘要： A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480.degree. C. The stop layer is then combined with an overlying dielectric layer to provide an inter-level dielectric structure through which a local interconnect can be formed to provide a conductive path to one or more regions of the underlying semiconductor devices.

摘要翻译： 沉积方法允许形成基本上没有由除气效应引起的缺陷的均匀的电介质停止层。 停止层沉积在高于至少480℃的常温的反应器室中。然后将停止层与覆盖的介电层组合以提供层间电介质结构，通过该层间电介质结构可以形成局部互连 为下面的半导体器件的一个或多个区域提供导电路径。

公开(公告)号：US6054735A

公开(公告)日：2000-04-25

申请号：US881498

申请日：1997-06-24

申请人： Minh Van Ngo

发明人： Minh Van Ngo

IPC分类号： C23C16/02 ,  C23C16/40 ,  C23C16/44 ,  H01L21/316 ,  H01L21/265

CPC分类号： H01L21/02164 ,  C23C16/0209 ,  C23C16/402 ,  C23C16/4404 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612

摘要： A very thin (less than 350 angstrom) layer of silicon dioxide (SiO.sub.2) is produced using plasma-enhanced chemical vapor deposition (PECVD) by substantially increasing the time duration of pre-coat and soak time steps of the PECVD process and substantially reducing the flow of silane (SiH.sub.4), the applied high frequency power and the applied pressure in the PECVD process.

摘要翻译： 使用等离子体增强化学气相沉积（PECVD）制造非常薄（小于350埃）的二氧化硅层（SiO 2），通过基本上增加PECVD工艺的预涂层和浸泡时间步骤的持续时间并显着减少 硅烷（SiH4）的流动，应用的高频功率和PECVD工艺中的施加压力。

公开(公告)号：US6027959A

公开(公告)日：2000-02-22

申请号：US993829

申请日：1997-12-18

申请人： William G. En ,  Minh Van Ngo ,  Olov B. Karlsson ,  Maria Chow Chan

发明人： William G. En ,  Minh Van Ngo ,  Olov B. Karlsson ,  Maria Chow Chan

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/335

CPC分类号： H01L29/6659 ,  H01L21/31116 ,  H01L29/6656 ,  H01L21/0276 ,  H01L21/32139

摘要： A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate during an etch back process associated with a nitride resistor protect etch process. The method includes removing a silicon oxynitride BARC, in-situ, during an oxide resistor protect etching process using a plasma formed with CF.sub.4 gas, CHF.sub.3 gas, O.sub.2 gas, and Argon (Ar) gas.

摘要翻译： 提供了一种在与氮化物电阻器保护蚀刻工艺相关的回蚀工艺期间从晶体管栅极去除底部抗反射涂层（BARC）的方法。 该方法包括在使用由CF 4气体，CHF 3气体，O 2气体和氩气（Ar）气体形成的等离子体的氧化物电阻保护蚀刻工艺期间原位去除氮氧化硅BARC。

公开(公告)号：US08647969B1

公开(公告)日：2014-02-11

申请号：US13362899

申请日：2012-01-31

申请人： Rinji Sugino ,  Yider Wu ,  Minh Van Ngo ,  Jeffrey Sinclair Glick ,  Kuo Tung Chang

发明人： Rinji Sugino ,  Yider Wu ,  Minh Van Ngo ,  Jeffrey Sinclair Glick ,  Kuo Tung Chang

IPC分类号： H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.

摘要翻译： 一种制造存储器件的方法包括在衬底上形成第一介电层，在第一介电层上形成电荷存储元件，并在电荷存储元件上形成栅极间电介质。 该方法还包括使用含氯的反应物在栅极间电介质上沉积硅控制栅极层。

公开(公告)号：US08133801B1

公开(公告)日：2012-03-13

申请号：US11189875

申请日：2005-07-27

申请人： Rinji Sugino ,  Yider Wu ,  Minh Van Ngo ,  Jeffrey Sinclair Glick ,  Kuo-Tung Chang

发明人： Rinji Sugino ,  Yider Wu ,  Minh Van Ngo ,  Jeffrey Sinclair Glick ,  Kuo-Tung Chang

IPC分类号： H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.

摘要翻译： 一种制造存储器件的方法包括在衬底上形成第一介电层，在第一介电层上形成电荷存储元件，并在电荷存储元件上形成栅极间电介质。 该方法还包括使用含氯的反应物在栅极间电介质上沉积硅控制栅极层。