公开(公告)号：US20140223226A1

公开(公告)日：2014-08-07

申请号：US13994609

申请日：2011-12-22

Applicant: Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrushnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/14

CPC classification number: G06F11/1405 ,  G06F11/1064

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Abstract translation: 描述了用于检测和校正处理器核心内的数据获取错误的装置和方法。 例如，用于检测和从数据获取错误中恢复的指令处理装置的一个实施例包括：具有多个指令处理阶段的至少一个处理器核心，包括数据获取阶段和退休阶段; 以及与处理级通信的错误处理逻辑，以执行以下操作：响应于由数据获取级执行的数据获取操作，检测与数据相关联的错误; 并且响应地执行一个或多个操作以确保该错误不会在退休阶段内破坏处理器核心的体系结构状态。

公开(公告)号：US20140189445A1

公开(公告)日：2014-07-03

申请号：US13728217

申请日：2012-12-27

Applicant: Ashok Raj ,  John G. Holm ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mohan J. Kumar

Inventor： Ashok Raj ,  John G. Holm ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mohan J. Kumar

IPC: G06F11/00

CPC classification number: G06F11/006 ,  G06F11/0715 ,  G06F11/0772 ,  G06F11/0793

Abstract: Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable indicator, and a second unit. The first unit is to detect a poison error. The programmable indicator is to indicate whether the poison error is signaled as a machine check error or as one of a fault and a system management interrupt. The second unit is to signal the poison error as one of a fault and a system management error responsive to the programmable indicator.

Abstract translation: 公开了用于信令软件可恢复错误的发明的实施例。 在一个实施例中，处理器包括第一单元，可编程指示器和第二单元。 第一个单位是检测毒物的错误。 可编程指示灯是指示是否发出毒物误差作为机器检查错误或作为故障和系统管理中断之一发出信号。 第二个单元将响应于可编程指示器的毒性错误信号作为故障之一和系统管理错误。

公开(公告)号：US20140143577A1

公开(公告)日：2014-05-22

申请号：US13997999

申请日：2011-12-22

Applicant: Murugasamy K. Nachimuthu ,  Mohan J. Kumar

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: G06F1/32 ,  G06F12/10 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0888 ,  G06F12/1027 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/60 ,  Y02D10/13 ,  Y02D10/14

Abstract: A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown.

Abstract translation: 描述了一种方法，其包括决定进入较低功率状态，以及关闭计算机系统中的存储器通道，响应其中计算机系统中的其他存储器通道保持活动，使得计算机在存储器通道关闭时保持工作。

公开(公告)号：US08671309B2

公开(公告)日：2014-03-11

申请号：US13175407

申请日：2011-07-01

Applicant: Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Theodros Yigzaw

Inventor： Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Theodros Yigzaw

IPC: G06F11/00

CPC classification number: G06F11/0715 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/0793 ,  G06F2211/1088

Abstract: Embodiments of a hardware processor including a plurality of machine state registers (MSRs) are described. At least one of the MSRs includes an erroring logical processing (ELP) bit which when set, indicates that a particular thread executing on the hardware processor caused an error.

Abstract translation: 描述了包括多个机器状态寄存器（MSR）的硬件处理器的实施例。 MSR中的至少一个包括错误的逻辑处理（ELP）位，当被设置时，指示在硬件处理器上执行的特定线程引起错误。

公开(公告)号：US20130326288A1

公开(公告)日：2013-12-05

申请号：US13997046

申请日：2011-12-31

Applicant: Shamanna M. Datta ,  Rajesh S. Parathasarathy ,  Mahesh S. Natu ,  Frank Binns ,  Mohan J. Kumar

Inventor： Shamanna M. Datta ,  Rajesh S. Parathasarathy ,  Mahesh S. Natu ,  Frank Binns ,  Mohan J. Kumar

IPC: G06F11/07

CPC classification number: G06F11/0754 ,  G06F12/1441 ,  G06F21/52

Abstract: A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting.

Abstract translation: 描述了一种方法，其包括通过将系统管理程序代码的存储器访问指令的目标存储器地址再次比较来检测系统管理模式程序代码的存储器访问尝试到达存储器的受保护区域之外的程序代码， 定义保护区域的范围。 该方法还包括响应于检测而提高误差信号。

公开(公告)号：US20130275810A1

公开(公告)日：2013-10-17

申请号：US13992506

申请日：2011-09-29

Applicant: Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

Inventor： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

IPC: G06F11/263

CPC classification number: G06F11/263 ,  G06F11/3664 ,  G06F11/3688

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Abstract translation: 公开了一种向存储器注入错误的装置和方法。 在一个实施例中，专用接口包括错误注入系统地址寄存器和耦合到错误注入系统地址寄存器的错误注入掩模寄存器。 如果错误注入系统地址寄存器包含与输入写入地址匹配的系统地址，则错误注入掩码寄存器会向存储器输出错误。

公开(公告)号：US20130212672A1

公开(公告)日：2013-08-15

申请号：US13837498

申请日：2013-03-15

Applicant: Shamanna M. Datta ,  Mohan J. Kumar

Inventor： Shamanna M. Datta ,  Mohan J. Kumar

IPC: G06F21/00

CPC classification number: G06F21/53 ,  G06F21/00 ,  G06F21/74 ,  G06F21/85

Abstract: Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.

Abstract translation: 描述了在微处理器系统中启动安全操作的方法和装置。 在一个实施例中，系统包括执行安全输入指令的处理器和芯片组，以使系统在执行安全输入指令期间进入静止状态。

公开(公告)号：US20130103938A1

公开(公告)日：2013-04-25

申请号：US13664930

申请日：2012-10-31

Applicant: Sham M. Datta ,  Mohan J. Kumar ,  Ernie Brickell ,  Ioannis T. Schoinas ,  James A. Sutton

Inventor： Sham M. Datta ,  Mohan J. Kumar ,  Ernie Brickell ,  Ioannis T. Schoinas ,  James A. Sutton

IPC: G06F21/00

CPC classification number: G06F21/57

Abstract: Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.

Abstract translation: 公开了用于重新配置安全系统的装置，方法和系统。 在一个实施例中，装置包括配置存储位置，锁定和锁定超驰逻辑。 配置存储位置是存储信息以配置设备。 该锁是为了防止写入配置存储位置。 锁定覆盖逻辑是允许从子操作模式代码执行的指令覆盖锁定。

公开(公告)号：US08364975B2

公开(公告)日：2013-01-29

申请号：US11648472

申请日：2006-12-29

Applicant: Mohan J. Kumar ,  Shay Gueron

Inventor： Mohan J. Kumar ,  Shay Gueron

IPC: H04L29/06

CPC classification number: G06F21/575 ,  G06F21/57 ,  G06F21/85

Abstract: An augmented boot code module includes instructions to be executed by a processing unit during a boot process. The augmented boot code module also includes an encrypted version of a cryptographic key that can be decrypted with a cryptographic key that remains in the processing unit despite a reset of the processing unit. In one embodiment, the processing unit may decrypt the encrypted version of the cryptographic key and then use the decrypted key to establish a protected communication channel with a security processor, such as a trusted platform module (TPM). Other embodiments are described and claimed.

Abstract translation: 增强引导代码模块包括在引导过程期间由处理单元执行的指令。 增强的引导代码模块还包括加密密钥的加密版本，其可以利用保留在处理单元中的加密密钥来解密，尽管处理单元的重置。 在一个实施例中，处理单元可以对加密密钥的加密版本进行解密，然后使用解密密钥与安全处理器（例如可信平台模块（TPM））建立受保护的通信信道。 描述和要求保护其他实施例。

公开(公告)号：US20130007507A1

公开(公告)日：2013-01-03

申请号：US13175407

申请日：2011-07-01

Applicant: Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Theodros Yigzaw

Inventor： Ashok Raj ,  Narayan Ranganathan ,  Mohan J. Kumar ,  Theodros Yigzaw

IPC: G06F11/00

CPC classification number: G06F11/0715 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/0793 ,  G06F2211/1088

Abstract: Embodiments of a hardware processor including a plurality of machine state registers (MSRs) are described. At least one of the MSRs includes an erroring logical processing (ELP) bit which when set, indicates that a particular thread executing on the hardware processor caused an error.

Abstract translation: 描述了包括多个机器状态寄存器（MSR）的硬件处理器的实施例。 MSR中的至少一个包括错误的逻辑处理（ELP）位，当被设置时，指示在硬件处理器上执行的特定线程引起错误。