Mixed lithography with dual resist and a single pattern transfer
    91.
    发明授权
    Mixed lithography with dual resist and a single pattern transfer 有权
    具有双光栅和单一图案转印的混合光刻

    公开(公告)号:US08334090B2

    公开(公告)日:2012-12-18

    申请号:US13015668

    申请日:2011-01-28

    IPC分类号: G03C5/00

    摘要: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.

    摘要翻译: 在碳基材料层或下层上形成无机电子束敏感氧化物层。 无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。 将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上,随后用紫外线照射并显影。 图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中,随后进入下层以形成沟槽。 碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模,并且之后可以容易地剥离。 随后去除图案化的紫外线敏感光刻胶,图案化氧化物区域和图案化的碳基材料层。

    Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric
    92.
    发明申请
    Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric 有权
    使用可牺牲图案电介质形成纳米线周围栅极的工艺

    公开(公告)号:US20120007051A1

    公开(公告)日:2012-01-12

    申请号:US12830514

    申请日:2010-07-06

    IPC分类号: H01L29/775 H01L21/84

    摘要: Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.

    摘要翻译: 提供了在纳米线FET器件中限定镶嵌栅极的技术。 一方面,提供一种制造FET器件的方法,包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 纳米线和焊盘以阶梯状构造在SOI层中图案化。 BOX凹入纳米线下方。 在凹入的BOX上形成可图案的电介质伪栅极,并围绕每个纳米线的一部分。 CMP停止层沉积在虚拟栅极和源极和漏极区域上。 在CMP停止层上沉积电介质膜。 使用CMP对电介质膜进行平面化以暴露虚拟栅极。 至少部分地去除虚拟栅极,以便在沟道区域中释放纳米线。 虚拟栅极被栅极导体材料代替。

    MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER
    93.
    发明申请
    MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER 有权
    具有双重电阻和单模式传输的混合光刻

    公开(公告)号:US20110123779A1

    公开(公告)日:2011-05-26

    申请号:US13015668

    申请日:2011-01-28

    IPC分类号: B32B3/10

    摘要: An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.

    摘要翻译: 在碳基材料层或下层上形成无机电子束敏感氧化物层。 无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。 将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上,随后用紫外线照射并显影。 图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中,随后进入下层以形成沟槽。 碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模,并且之后可以容易地剥离。 随后去除图案化的紫外线敏感光刻胶,图案化氧化物区域和图案化的碳基材料层。

    PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES
    94.
    发明申请
    PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES 审中-公开
    等离子体固化材料的等离子体刻蚀特性

    公开(公告)号:US20090174036A1

    公开(公告)日:2009-07-09

    申请号:US11969525

    申请日:2008-01-04

    IPC分类号: H01L29/30 G03F7/26

    CPC分类号: G03F7/40

    摘要: A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing.

    摘要翻译: 公开了一种能够在光刻图案化之后显着降低线边缘粗糙度(LER)和线宽粗糙度(LEW)来制造半导体器件(即STI结构,栅极和互连)的方法。 本发明的方法需要使用含有等离子体的惰性物质来调整光刻后的真空紫外(VUV)发射和/或给定特征(在相同的蚀刻平台上)的一个蚀刻工艺,以引发增加的交联 的一个或多个图案形成材料,因此能够提高耐蚀刻性和减少LER和LEW后蚀刻处理。

    Carbon containing tips with cylindrically symmetrical carbon containing expanded bases
    98.
    发明授权
    Carbon containing tips with cylindrically symmetrical carbon containing expanded bases 有权
    含碳圆顶对称含碳膨胀基底碳

    公开(公告)号:US07109515B2

    公开(公告)日:2006-09-19

    申请号:US10715057

    申请日:2003-11-17

    IPC分类号: H01L29/06

    摘要: Systems and methods are described for carbon containing tips with cylindrically symmetrical carbon containing expanded bases. A method includes producing an expanded based carbon containing tip including: fabricating a carbon containing expanded base on a substrate; and then fabricating a carbon containing fiber on the expanded base. An apparatus includes a carbon containing expanded base coupled to a substrate; and a carbon containing extension coupled to said carbon containing expanded base. The carbon containing expanded base is substantially cylindrically symmetrical and said carbon containing extension is substantially cylindrically symmetrical.

    摘要翻译: 对具有圆柱形对称的含碳膨胀基底的含碳尖端描述了系统和方法。 一种方法包括制备基于膨胀的含碳尖端,其包括:在基底上制造含碳膨胀的基底; 然后在膨胀的基底上制造含碳纤维。 一种装置包括:与基底耦合的含碳膨胀基底; 和与所述含碳膨胀的基底相连的含碳延伸部分。 含碳膨胀基部基本上是圆柱形对称的,并且所述含碳延伸部基本上是圆柱形对称的。

    Single self-aligned carbon containing tips
    99.
    发明授权
    Single self-aligned carbon containing tips 失效
    单个自对准含碳尖端

    公开(公告)号:US06692324B2

    公开(公告)日:2004-02-17

    申请号:US09810531

    申请日:2001-03-15

    IPC分类号: H01J902

    摘要: Systems and methods are described for a single self-aligned carbon nanofiber emitters within a dielectric well. A method, includes: providing a substrate; defining lithographically a catalyst particle, the catalyst particle coupled to the substrate; depositing a dielectric layer, the dielectric layer coupled to the substrate; depositing an extractor layer, the extractor layer coupled to the dielectric layer; forming an extractor aperture in the extractor layer; forming a dielectric well in the dielectric layer to uncover the catalyst particle; and then fabricating at a location of the catalyst particle and within the dielectric well a single self-aligned carbon containing tip i) having a base located substantially at the bottom of the dielectric well and ii) extending substantially away from the substrate using plasma enhanced chemical vapor deposition.

    摘要翻译: 描述了电介质井内单个自对准碳纳米纤维发射体的系统和方法。 一种方法,包括:提供基底; 以平版印刷催化剂颗粒,所述催化剂颗粒耦合到所述基材; 沉积介电层,所述电介质层耦合到所述衬底; 沉积提取器层,所述提取器层耦合到所述电介质层; 在提取器层中形成提取器孔; 在介电层中形成电介质阱以露出催化剂颗粒; 然后在催化剂颗粒的位置和电介质阱内制造单个自对准含碳尖端i),其具有基本位于电介质阱底部的基部,以及ii)使用等离子体增强化学品基本上远离衬底延伸 气相沉积。