公开(公告)号：US09245871B2

公开(公告)日：2016-01-26

申请号：US13857077

申请日：2013-04-04

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh

IPC: G06F11/22 ,  G06F17/50 ,  H01L25/065 ,  G11C5/02 ,  G11C8/12 ,  G11C16/20 ,  H01L23/48 ,  H01L25/18

CPC classification number: H01L25/0657 ,  G06F17/5077 ,  G11C5/02 ,  G11C8/12 ,  G11C16/20 ,  H01L23/481 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.

Abstract translation: 公开了具有芯片标识符结构的可垂直堆叠的管芯。 在一个具体实施例中，公开了一种半导体器件，其包括具有第一至第二硅通孔的管芯以传送芯片标识符和其它数据。 半导体器件还包括芯片标识符结构，其包括至少两个穿过硅通孔，每个硅通孔硬接线到外部电触头。

公开(公告)号：US09239788B2

公开(公告)日：2016-01-19

申请号：US14062558

申请日：2013-10-24

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong ,  Xiaochun Zhu ,  Jungwon Suh

IPC: G06F12/08 ,  G11C7/10 ,  G11C11/16 ,  G06F13/00

CPC classification number: G06F12/0802 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/0864 ,  G06F2212/1016 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/60 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1084 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0002 ,  G11C2207/2245 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

公开(公告)号：US09224467B2

公开(公告)日：2015-12-29

申请号：US14147817

申请日：2014-01-06

Applicant: QUALCOMM Incorporated

Inventor： Wuyang Hao ,  Jungwon Suh ,  Kangho Lee ,  Taehyun Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74

Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

Abstract translation: 基于电阻的存储器包括二极管接入设备。 在特定实施例中，一种方法包括利用第一电​​压来偏置位线。 该方法还包括利用第二电压来偏置感测线。 偏置位线并偏置感测线通过电阻型存储元件并通过第一二极管和第二二极管之一产生电流。 第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

公开(公告)号：US20140177325A1

公开(公告)日：2014-06-26

申请号：US13721092

申请日：2012-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Jungwon Suh

IPC: G11C11/16

CPC classification number: G11C11/16 ,  G11C11/1653 ,  G11C2211/5643 ,  Y10T29/49117

Abstract: Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability.

Abstract translation: 用于集成磁阻随机存取存储器（MRAM）模块的系统和方法。 集成电路包括处理器，其中没有集成在第一芯片上的最后一级高速缓存，MRAM模块包括MRAM最后一级高速缓存和集成在第二芯片上的MRAM主存储器，其中MRAM模块是制造为单片封装或 多个包装。 第二包还包括存储器控制器逻辑。 简化的接口结构被配置为耦合第一和第二封装。 MRAM模块设计用于高速，高数据保留，MRAM最后一级缓存和MRAM主内存之间的积极预取，改进的页面处理和改进的封印能力。

公开(公告)号：US20130326188A1

公开(公告)日：2013-12-05

申请号：US13752427

申请日：2013-01-29

Applicant: QUALCOMM INCORPORATED

Inventor： Jungwon Suh ,  Dexter T. Chun

IPC: G06F12/10

CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C5/063 ,  G11C7/02 ,  G11C7/222 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.

Abstract translation: 在一个实施例中，堆叠封装的封装系统具有存储器管芯和逻辑管芯。 存储器管芯包括第一存储器和第二存储器，每个存储器和第二存储器分别独立于另一个存储器和第二存储器，并且每个具有电连接到逻辑管芯的芯片间接口。 逻辑管芯具有两个独立的时钟源，一个用于向第一存储器提供第一时钟信号，另一个时钟源提供第二时钟信号给第二存储器。