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    BOOSTING READ SCHEME WITH BACK-GATE BIAS
    92.
    发明申请
    BOOSTING READ SCHEME WITH BACK-GATE BIAS 有权

    公开(公告)号：US20210174881A1

    公开(公告)日：2021-06-10

    申请号：US17173023

    申请日：2021-02-10

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34

    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

    HOT-COLD VTH MISMATCH USING VREAD MODULATION
    95.
    发明申请
    HOT-COLD VTH MISMATCH USING VREAD MODULATION 审中-公开

    公开(公告)号：US20200321061A1

    公开(公告)日：2020-10-08

    申请号：US16909830

    申请日：2020-06-23

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Dae Wung Kang ,  Peter Rabkin ,  Masaaki Higashitani

    IPC: G11C16/26 ,  G11C7/04 ,  G11C16/04 ,  G11C11/4074 ,  G11C11/56

    Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.

    NAND boosting using dynamic ramping of word line voltages
    98.
    发明授权
    NAND boosting using dynamic ramping of word line voltages 有权

    公开(公告)号：US10297329B2

    公开(公告)日：2019-05-21

    申请号：US15352390

    申请日：2016-11-15

    Applicant: SanDisk Technologies LLC

    Inventor： Peter Rabkin ,  Yingda Dong ,  Masaaki Higashitani

    IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

    Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.

    Offset backside contact via structures for a three-dimensional memory device
    100.
    发明授权
    Offset backside contact via structures for a three-dimensional memory device 有权

    公开(公告)号：US10103161B2

    公开(公告)日：2018-10-16

    申请号：US15195377

    申请日：2016-06-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Fumitoshi Ito ,  Masaaki Higashitani ,  Cheng-Chung Chu ,  Jayavel Pachamuthu ,  Tuan Pham

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/535 ,  H01L29/06

    Abstract: Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

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