公开(公告)号：US06232163B1

公开(公告)日：2001-05-15

申请号：US09362549

申请日：1999-07-28

申请人： Steven H. Voldman ,  Robert J. Gauthier, Jr. ,  Jeffrey S. Brown

发明人： Steven H. Voldman ,  Robert J. Gauthier, Jr. ,  Jeffrey S. Brown

IPC分类号： H01L218238

CPC分类号： H01L27/0811 ,  H01L29/7391 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.

摘要翻译： 用于混合电压，混合信号和模拟/数字应用的高耐压二极管结构。 优选的硅二极管包括在半导体（硅）层或主体上的至少一个电介质膜层上的多晶硅栅极结构。 阱体或植入区域形成在SOI半导体衬底或SOI晶片的表面硅层中。 施加到多晶硅栅极膜的电压，电耗电，降低电介质膜两端的电压。 本征多晶硅膜可以是反掺杂的，注入低掺杂注入，注入低掺杂源/漏注入，或者与低掺杂的MOSFET LDD或延伸注入。 或者，当限定耗尽多晶硅栅极硅二极管以形成低串联电阻二极管植入物时，可以在栅极结构上形成块掩模，防止膜过度掺杂。 可选地，可以使用混合光致抗蚀剂方法在硅中形成更高掺杂的边缘注入，以减少二极管串联电阻而不使用块掩模。

公开(公告)号：US6034388A

公开(公告)日：2000-03-07

申请号：US79846

申请日：1998-05-15

申请人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

IPC分类号： H01L21/334 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/12 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L29/66181 ,  H01L21/76237 ,  H01L21/76264 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/94 ,  H01L21/76283 ,  Y10S257/907

摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.

摘要翻译： 一种包括半导体衬底的电路元件。 第一导电类型的阱区形成在衬底的表面中。 在基板上形成电介质膜。 在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。 栅极导体由多晶硅膜形成。 栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 在栅极导体的每一侧上形成多晶硅边缘隔离物。 第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。 多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。 第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。 应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。

公开(公告)号：US08906751B2

公开(公告)日：2014-12-09

申请号：US12985840

申请日：2011-01-06

申请人： Michel J. Abou-Khalil ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li

发明人： Michel J. Abou-Khalil ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li

IPC分类号： H01L21/332 ,  H01L29/66 ,  H01L27/02 ,  H01L29/08 ,  H01L29/74

CPC分类号： H01L27/0262 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0839 ,  H01L29/66393 ,  H01L29/7436

摘要： Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.

摘要翻译： 本文公开了可控硅整流器（SCR），制造方法和设计结构。 该方法包括在绝缘体上硅（SOI）晶片的掩埋绝缘体层上形成公共P阱。 该方法还包括在P阱中形成多个可控硅整流器（SCR），使得多个SCR中的每一个的N +扩散阴极通过公共P阱耦合在一起。

公开(公告)号：US08680573B2

公开(公告)日：2014-03-25

申请号：US13455653

申请日：2012-04-25

申请人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li

发明人： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Junjun Li

IPC分类号： H01L29/66

CPC分类号： H01L21/8222 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

摘要： Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region.

摘要翻译： 可控硅整流器的器件结构，设计结构和制造方法。 第一导电类型的阱形成在器件区域中，其可以由绝缘体上半导体衬底的器件层限定。 在井中形成第二导电类型的掺杂区域。 在器件区域中形成可控硅整流器的阴极和二极管的阴极。 可控硅整流器包括阱的第一部分和由掺杂区域的第一部分组成的阳极。 二极管包括阱的第二部分和由掺杂区域的第二部分组成的阳极。

公开(公告)号：US08614121B2

公开(公告)日：2013-12-24

申请号：US13306488

申请日：2011-11-29

申请人： Robert J. Gauthier, Jr. ,  Junjun Li

发明人： Robert J. Gauthier, Jr. ,  Junjun Li

IPC分类号： H01L21/00

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： Back gate triggered silicon controlled rectifiers (SCR) and methods of manufacture are disclosed. The method includes forming a first diffusion type and a second diffusion type in a semiconductor layer of a silicon on insulator (SOI) substrate. The method further includes forming a back gate of a first diffusion type in a substrate under an insulator layer of the SOI substrate. The method further includes forming raised diffusion regions of a first dopant type and a second dopant type, adjacent to the second diffusion type and the first diffusion type, respectively. The back gate is formed to cover the second diffusion type, the first diffusion type and the second dopant type of the raised diffusion regions.

摘要翻译： 背栅触发硅控整流器（SCR）及其制造方法。 该方法包括在绝缘体上硅（SOI）衬底的半导体层中形成第一扩散型和第二扩散型。 该方法还包括在SOI衬底的绝缘体层之下的衬底中形成第一扩散型的背栅。 该方法还包括分别形成与第二扩散型和第一扩散型相邻的第一掺杂剂类型和第二掺杂剂类型的凸起扩散区域。 后栅极形成为覆盖第二扩散型，第一扩散型和第二掺杂型的凸起扩散区。

公开(公告)号：US08598660B2

公开(公告)日：2013-12-03

申请号：US13150612

申请日：2011-06-01

申请人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, Jr. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

发明人： Renata Camillo-Castillo ,  Erik Mattias Dahlstrom ,  Robert J. Gauthier, Jr. ,  Ephrem G. Gebreselasie ,  Richard A. Phelps ,  Jed Hickory Rankin ,  Yun Shi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66492 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7843

摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.

公开(公告)号：US08513738B2

公开(公告)日：2013-08-20

申请号：US13188094

申请日：2011-07-21

申请人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

发明人： John B. Campi, Jr. ,  Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Junjun Li ,  Rahul Mishra ,  Mujahid Muhammad

IPC分类号： H01L23/60

CPC分类号： H01L29/41775 ,  H01L27/0266 ,  H01L29/1087 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

摘要翻译： 静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。 第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。 可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。 静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

公开(公告)号：US08216909B2

公开(公告)日：2012-07-10

申请号：US12547529

申请日：2009-08-26

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti ,  Yun Shi

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti ,  Yun Shi

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.

摘要翻译： 一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。 门通过气隙与身体的至少一部分分离。 气隙也在第一平面。

公开(公告)号：US08169760B2

公开(公告)日：2012-05-01

申请号：US12355889

申请日：2009-01-19

申请人： Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad

发明人： Shunhua T. Chang ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Mujahid Muhammad

IPC分类号： H02H9/00 ,  H02H3/22 ,  H02H3/20

CPC分类号： H01L27/0266

摘要： An integrated circuit, design structures and methods of forming the integrated circuit which includes a signal pad ESD coupled to an I/O signal pad and a power supply ESD coupled to a source VDD. The signal pad ESD and the power supply ESD are integrated in a single ESD structure.

摘要翻译： 集成电路，形成集成电路的设计结构和方法，其包括耦合到I / O信号焊盘的信号焊盘ESD和耦合到源VDD的电源ESD。 信号垫ESD和电源ESD集成在单个ESD结构中。

公开(公告)号：US08039868B2

公开(公告)日：2011-10-18

申请号：US12342228

申请日：2008-12-23

申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Aniket Srivastava

发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Aniket Srivastava

IPC分类号： H01L29/72 ,  H01L29/74

CPC分类号： H01L29/66386 ,  H01L24/06 ,  H01L27/0262 ,  H01L29/74 ,  H01L29/7436 ,  H01L2224/05554 ,  H01L2924/14 ,  H01L2924/00

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. Further, the first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.

摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括形成在衬底中的第一和第二可控硅整流器（SCR）。 此外，第一和第二SCR各自包括在第一和第二SCR之间共同共享的至少一个部件。