公开(公告)号：US20120135587A1

公开(公告)日：2012-05-31

申请号：US13357656

申请日：2012-01-25

申请人： Jee Hwan Kim ,  Stephen W. Bedell ,  Siegfried Maurer ,  Devendra K. Sadana

发明人： Jee Hwan Kim ,  Stephen W. Bedell ,  Siegfried Maurer ,  Devendra K. Sadana

IPC分类号： H01L21/265

CPC分类号： H01L21/26513 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  Y10S438/919

摘要： A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached.

摘要翻译： 公开了一种在半导体中产生n型载流子的方法。 该方法包括提供具有原子半径的半导体。 将n型掺杂物种植入半导体，其中n型掺杂剂物质具有掺杂剂原子半径。 将补偿物种植入到半导体中，补偿物质具有补偿原子半径。 以使得半导体原子半径的尺寸在掺杂剂原子半径和补偿原子半径之间的方式选择n型掺杂物种类和补偿种类。 公开了用于在锗（Ge）中生成n型载流子的另一种方法。 该方法包括设定载体的目标浓度，将一定剂量的n型掺杂剂物质注入到Ge中，并选择与目标载体浓度分数相对应的剂量。 对Ge进行热退火，以激活n型掺杂物种类并修复至少一部分注入损伤。 重复注入和热退火直到目标n型载流子浓度达到。

公开(公告)号：US20110175166A1

公开(公告)日：2011-07-21

申请号：US12689339

申请日：2010-01-19

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/7849

摘要： A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.

摘要翻译： 半导体器件和制造方法包括在一个轴上具有应变的应变半导体层。 在半导体层中形成长鳍片和短鳍片，使得长鳍片沿着一个轴线具有应变长度。 在长鳍片上形成n型晶体管，在该至少一个短鳍片上形成p型晶体管。 n型晶体管中的应变提高了性能。

公开(公告)号：US20110175164A1

公开(公告)日：2011-07-21

申请号：US12689346

申请日：2010-01-19

申请人： Stephen W. Bedell ,  Huiming Bu ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Chun-chen Yeh

发明人： Stephen W. Bedell ,  Huiming Bu ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Chun-chen Yeh

IPC分类号： H01L27/12 ,  H01L21/86

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.

摘要翻译： 一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构 在活跃地区。 在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

公开(公告)号：US07679141B2

公开(公告)日：2010-03-16

申请号：US12027561

申请日：2008-02-07

申请人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Huajie Chen ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Richard J. Murphy ,  Devendra K. Sadana

IPC分类号： H01L31/392

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L21/7624 ,  H01L21/76254 ,  H01L29/1054

摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

摘要翻译： 提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。 该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。 然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。 加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。 此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。 在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。 该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

公开(公告)号：US06989058B2

公开(公告)日：2006-01-24

申请号：US10654232

申请日：2003-09-03

申请人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： C30B25/02

CPC分类号： H01L21/7624 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/24917

摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

摘要翻译： 在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化 温度。 因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

公开(公告)号：US06878611B2

公开(公告)日：2005-04-12

申请号：US10336147

申请日：2003-01-02

申请人： Devendra K. Sadana ,  Stephen W. Bedell ,  Tze-Chiang Chen ,  Kwang Su Choe ,  Keith E. Fogel

发明人： Devendra K. Sadana ,  Stephen W. Bedell ,  Tze-Chiang Chen ,  Kwang Su Choe ,  Keith E. Fogel

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/36

CPC分类号： H01L21/324 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02694 ,  H01L21/823807 ,  Y10S438/96

摘要： In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.

摘要翻译： 在本发明的优选实施例中，描述了通过SiGe / SOI热混合工艺将图案化SOI区域转换为图案化SGOI（氧化硅上的硅 - 锗）的方法，以进一步增强嵌入式DRAM中逻辑电路的性能。 SGOI区域用作随后的Si生长的模板，使得Si被应变，并且Si中的电子和空穴具有较高的迁移率。

公开(公告)号：US06841457B2

公开(公告)日：2005-01-11

申请号：US10196611

申请日：2002-07-16

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L29/161 ,  H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/36

CPC分类号： H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02664 ,  Y10S438/933

摘要： A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlying barrier layer that is resistant to Ge diffusion. Next, ions that are capable of forming defects that allow mechanical decoupling at or near said interface are implanted into the structure and thereafter the structure including the implanted ions is subjected to a heating step which permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe layer to form a substantially relaxed, single crystal and homogeneous SiGe layer atop the barrier layer. SiGe-on-insulator substrates having the improved properties as well as heterostructures containing the same are also provided.

公开(公告)号：US06803240B1

公开(公告)日：2004-10-12

申请号：US10654231

申请日：2003-09-03

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L21302

CPC分类号： G01N21/9501 ,  G01N21/9505 ,  G01N2021/8461

摘要： Described herein is a method for delineating crystalline defects in a thin Si layer over a SiGe alloy layer. The method uses a defect etchant with a high-defect selectivity in Si. The Si is etched downed to a thickness that allows the defect pits to reach the underlying SiGe layer. A second etchant, which can be the same or different from the defect etchant, is then used which attacks the SiGe layer under the pits while leaving Si intact.

摘要翻译： 这里描述了一种在SiGe合金层上描绘薄Si层中的晶体缺陷的方法。 该方法在Si中具有高缺陷选择性的缺陷蚀刻剂。 将Si蚀刻到允许缺陷凹坑到达下面的SiGe层的厚度。 然后使用可以与缺陷蚀刻剂相同或不同的第二蚀刻剂，其在凹陷下攻击SiGe层，同时保持Si完整。

公开(公告)号：US08709957B2

公开(公告)日：2014-04-29

申请号：US13481062

申请日：2012-05-25

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Ibrahim Alhomoudi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Ibrahim Alhomoudi

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/304 ,  B81C99/008 ,  H01L21/02002

摘要： A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.

摘要翻译： 利用位于基底的最上表面的一部分但不是全部的至少一个应力层部分剥离基底基板的局部区域的方法。 该方法包括提供具有均匀厚度的基底基底和跨越整个基底基底的平面最上表面。 至少一个具有形状的应力层部分形成在基底基板的最上表面的至少一部分但不是全部。 进行剥离，其从基底基板移除材料层部分并提供剩余的基底部分。 材料层部分具有至少一个应力层部分的形状，而剩余的基底部分具有位于其中的至少一个与至少一个应力层的形状相关的开口。

公开(公告)号：US08709914B2

公开(公告)日：2014-04-29

申请号：US13159893

申请日：2011-06-14

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/304 ,  H01L31/1896 ,  Y02E10/50 ,  Y02P80/30

摘要： A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate.

摘要翻译： 提供了一种受控层转移的方法。 该方法包括向基底基底提供应力层。 应力层具有位于基底基板的上表面顶部的应力层，以及位于基底基板的每个侧壁边缘附近的自锁紧应力层。 然后将剥落抑制剂施加在基底衬底的应力层部分的顶部，然后将应力层的自锁定应力层部分与应力层部分分离。 位于应力层部分之下的基底部分的一部分然后从原始基底剥离。 剥落包括从应力层部分顶部置换剥落抑制剂。 剥落后，从基底基板的剥离部的顶部除去应力层。