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138 条记录 (耗时 0.028 秒)

    Cache based physical layer self test
    96.
    发明申请
    Cache based physical layer self test 有权
    基于缓存的物理层自检

    公开(公告)号：US20060005092A1

    公开(公告)日：2006-01-05

    申请号：US10882966

    申请日：2004-06-30

    申请人： Tim Frodsham ,  Lakshminarayan Krishnamurty ,  Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Theodore Schoenborn

    发明人： Tim Frodsham ,  Lakshminarayan Krishnamurty ,  Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Theodore Schoenborn

    IPC分类号： G01R31/28

    CPC分类号： G06F11/27

    摘要： A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output (“I/O”) unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

    摘要翻译： 从处理器的缓存执行软件自检引擎。 使用处理器的执行引擎执行软件自检引擎，以执行物理层自检。 通过在自检引擎的控制下将来自执行引擎的测试向量发送到处理器的输入/输出（“I / O”）单元，沿着将执行引擎耦合到I / O的数据通路执行物理层自检， O单位。 测试向量沿着包括I / O单元和数据通路的环回路径传输，以沿着循环路径测试硬件设备。

    Method and apparatus of lowering I/O bus power consumption
    98.
    发明申请
    Method and apparatus of lowering I/O bus power consumption 审中-公开
    降低I / O总线功耗的方法和装置

    公开(公告)号：US20050144488A1

    公开(公告)日：2005-06-30

    申请号：US10810119

    申请日：2004-03-25

    申请人： Victor Lee ,  Phanindra Mannava ,  Akhilesh Kumar ,  Sanjay Dabral

    发明人： Victor Lee ,  Phanindra Mannava ,  Akhilesh Kumar ,  Sanjay Dabral

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3209 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

    摘要： The current method and apparatus provides a novel approach to manage the power consumption of a high speed I/O interface by selectively turning off non-essential portions of the interface. Here only part of the interface is powered off as compared to the whole interface being turned off. From the upper layers (protocol/system) perspective, the interface is always “on”. Thus, this mechanism reduces link power by selectively turning off portions of the link, yet allowing for fast wake up in an interface power management architecture.

    摘要翻译： 目前的方法和装置提供了一种新颖的方法，通过选择性地关闭界面的非必要部分来管理高速I / O接口的功耗。 与整个接口关闭相比，这里只有部分接口掉电。 从上层（协议/系统）的角度来看，界面总是“开”。 因此，该机制通过选择性地关闭链路的部分而减少链路功率，但允许在接口电源管理架构中快速唤醒。

    Method and apparatus for a linearized output driver and terminator
    99.
    发明授权
    Method and apparatus for a linearized output driver and terminator 有权
    线性化输出驱动器和终端器的方法和装置

    公开(公告)号：US06646324B1

    公开(公告)日：2003-11-11

    申请号：US09609434

    申请日：2000-06-30

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L2900

    CPC分类号： H01L29/66659 ,  H01L29/7835 ,  Y02P80/30

    摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

    摘要翻译： 描述了用于线性化输出驱动器和终止器的方法和装置。 在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。 该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。 该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。 该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器 基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。

    Low cost and high speed 3-load printed wiring board bus topology
    100.
    发明授权
    Low cost and high speed 3-load printed wiring board bus topology 有权
    低成本和高速3负载印刷线路板总线拓扑

    公开(公告)号：US06417462B1

    公开(公告)日：2002-07-09

    申请号：US09596613

    申请日：2000-06-19

    申请人： Sanjay Dabral ,  Ming Zeng

    发明人： Sanjay Dabral ,  Ming Zeng

    IPC分类号： H01R909

    CPC分类号： H05K1/0246 ,  G06F13/4086 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49155

    摘要： A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units having twin processors and a bridge chip set, yielding a motherboard having significantly lower number of metal layers, a faster bus and significantly improved noise margin, all with high density IC packages on a wide parallel bus.

    摘要翻译： 公开了一种具有3负载拓扑结构的多层印刷电路板。 具有第一，第二和第三组端子的第一，第二和第三集成电路（IC）印刷电路板封装分别安装在板的相对侧上，使得第二组端子与第三组端子正对。 每个封装包含耦合到相应的一组端子的IC管芯。 第一封装中的IC管芯基本上与第二封装中包含的IC管芯相同，并且与第三封装件中包含的IC管芯不同。 为了改善将第一封装与第二和第三封装互连的金属线的扇出，将封装中的第一组，第二组和第三组端子中的每一个布置成大致U形。 每组终端具有由板中的金属线实现的并行总线的相同的一组信号分配。 3负载拓扑结构对于具有双处理器和桥接芯片组的个人计算机主板单元特别有用，产生具有显着更低数量金属层的母板，更快的总线和显着改善的噪声容限，所有这些都具有高密度IC封装 宽并行总线。