公开(公告)号：US10572255B2

公开(公告)日：2020-02-25

申请号：US15636681

申请日：2017-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/02 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.

公开(公告)号：US20190121697A1

公开(公告)日：2019-04-25

申请号：US16133434

申请日：2018-09-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F11/10 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F11/00 ,  G06F12/0817 ,  G06F12/0875 ,  G06F11/14

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US10162641B2

公开(公告)日：2018-12-25

申请号：US15429205

申请日：2017-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F9/312 ,  G06F12/12 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/10

Abstract: This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

公开(公告)号：US20160188408A1

公开(公告)日：2016-06-30

申请号：US14587234

申请日：2014-12-31

Applicant: Texas Instruments Incorporated

Inventor： Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  David M. Thompson ,  Jonathan (Son) Hung Tran

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

Abstract: This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time.

Abstract translation: 本发明是数据处理装置和方法。 通过产生对应于该数据的纠错码，使用纠错码来防止数据损坏。 在本发明中，将数据和相应的纠错码转发到另一组寄存器，而不用再生纠错码或使用纠错码进行错误检测或校正。 只有以后才采取纠错检测和纠正措施。 在数据处理装置中不同的数据/纠错码寄存器可能处于不同的流水线相位。 本发明通过携带数据的整个数据路径转发具有数据的纠错码。 本发明为整个数据路径提供错误保护，而不需要大量硬件或额外的时间。

公开(公告)号：US09239735B2

公开(公告)日：2016-01-19

申请号：US14334352

申请日：2014-07-17

Applicant: Texas Instruments Incorporated

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Q. Bui ,  Mel A. Phipps ,  Todd T. Hahn

IPC: G06F9/45 ,  G06F9/48 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F8/30 ,  G06F8/443 ,  G06F8/4442 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3842

Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract translation: 在需要数据之前，静态调度处理器编译器会在程序中调度一个推测性负载。 在程序行为由于推测负载而变化之前，编译器会插入一条条件指令来确认或不肯定推测负载。 该条件不仅仅基于推测负载地址是否正确，而且还包括根据原始源代码的依赖性。 编译器可以与正交条件并行地静态安排两个或更多个分支。

公开(公告)号：US20150026444A1

公开(公告)日：2015-01-22

申请号：US14334352

申请日：2014-07-17

Applicant: Texas Instruments Incorporated

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Q. Bui ,  Mel A. Phipps ,  Todd T. Hahn

IPC: G06F9/30 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F8/30 ,  G06F8/443 ,  G06F8/4442 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3842

Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract translation: 在需要数据之前，静态调度处理器编译器会在程序中调度一个推测性负载。 在程序行为由于推测负载而变化之前，编译器会插入一条条件指令来确认或不肯定推测负载。 该条件不仅仅基于推测负载地址是否正确，而且还包括根据原始源代码的依赖性。 编译器可以与正交条件并行地静态安排两个或更多个分支。

公开(公告)号：US20150019835A1

公开(公告)日：2015-01-15

申请号：US14327038

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885

Abstract: A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.

Abstract translation: 矢量处理器的预测方法，通过使用单独的条件代码扩展来最大限度地减少大多数指令中嵌入谓词字段的使用。 专用谓词寄存器提供向量指令的精细粒度预测，其中谓词寄存器的每个位控制向量数据的8位。

公开(公告)号：US12235773B2

公开(公告)日：2025-02-25

申请号：US17158095

申请日：2021-01-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Son H. Tran

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/06 ,  G06F15/78

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.

公开(公告)号：US12099843B2

公开(公告)日：2024-09-24

申请号：US18120601

申请日：2023-03-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Zbiciak ,  Sahithi Krishna ,  Soujanya Narnur

IPC: G06F9/30 ,  G06F12/0811

CPC classification number: G06F9/3016 ,  G06F9/30065 ,  G06F9/30098 ,  G06F12/0811

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US20240202123A1

公开(公告)日：2024-06-20

申请号：US18594091

申请日：2024-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0815 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F15/80

CPC classification number: G06F12/0815 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3853 ,  G06F9/3887 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30065 ,  G06F9/325 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/6026 ,  G06F2212/621

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.