公开(公告)号：US07177179B2

公开(公告)日：2007-02-13

申请号：US10512545

申请日：2003-04-21

申请人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Hideaki Numata ,  Kiyotaka Tsuji

发明人： Sadahiko Miura ,  Tadahiko Sugibayashi ,  Hideaki Numata ,  Kiyotaka Tsuji

IPC分类号： G11C11/14

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/16

摘要： A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the upper surface side of the substrate, memory cells, and plugs penetrating the interlayer insulation film. The memory cell includes a first magnetic layer formed on the upper surface side of the interlayer insulation film, a tunnel insulation layer formed on the first magnetic layer, and a second magnetic layer formed on the tunnel insulation layer. The plug is connected electrically with the first magnetic layer. The tunnel current passing part of the tunnel insulation layer located between the first and second magnetic layers is arranged, at least partially, so as not to overlap the plug in the direction perpendicular to the surface of the substrate.

摘要翻译： 一种用于消除磁隧道结隧道绝缘膜中的缺陷并用于抑制在存储器中使用磁性隧道结的MRAM中的有缺陷位的产生的技术。 磁性存储器包括基板，覆盖基板的上表面侧的层间绝缘膜，存储单元和穿透层间绝缘膜的插塞。 存储单元包括形成在层间绝缘膜的上表面侧的第一磁性层，形成在第一磁性层上的隧道绝缘层和形成在隧道绝缘层上的第二磁性层。 插头与第一磁性层电连接。 位于第一和第二磁性层之间的隧道绝缘层的隧道电流通过部分被布置成至少部分地不与垂直于衬底的表面的方向上的插塞重叠。

公开(公告)号：US06526541B2

公开(公告)日：2003-02-25

申请号：US09873708

申请日：2001-06-04

申请人： Tadahiko Sugibayashi

发明人： Tadahiko Sugibayashi

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： For use in designing a logic circuit of a semiconductor device, a library (10) memorizes not only a delay value (TYP, MIN, or MAX) for each of signal paths of a circuit element of the logic circuit but also a standard deviation (&sgr;CHIP or &sgr;TR) of a variation of the delay value for each of the signal paths of the circuit element. Instead of the standard deviation, the library may memorize a variance of the variation. The variance is given by (&sgr;CHIP)2 or ( &sgr;TR)2 when the variation is a normal distribution.

摘要翻译： 为了用于设计半导体器件的逻辑电路，库（10）不仅存储逻辑电路的电路元件的每个信号路径的延迟值（TYP，MIN或MAX），而且还存储标准偏差（ sigmaCHIP或sigmaTR）电路元件的每个信号路径的延迟值的变化。 而不是标准偏差，库可以记住变化的方差。 当变化是正态分布时，方差由（sigmaCHIP）2或（sigmaTR）2给出。

公开(公告)号：US06515511B2

公开(公告)日：2003-02-04

申请号：US09785089

申请日：2001-02-16

申请人： Tadahiko Sugibayashi ,  Tohru Mogami

发明人： Tadahiko Sugibayashi ,  Tohru Mogami

IPC分类号： H03K19177

CPC分类号： H01L27/1203 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/1214

摘要： A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.

摘要翻译： 半导体集成电路器件具有多个基本单元。 将基本电池放置成矩阵形式，并形成在半导体衬底上。 每个基本单元包括导线选择部分和逻辑门部分。 逻辑门部分具有MOS晶体管。 导线选择部分具有用作转移栅极的薄膜晶体管。 电线选择部分经由层间绝缘膜放置在逻辑门部分上。

公开(公告)号：US5732026A

公开(公告)日：1998-03-24

申请号：US713692

申请日：1996-09-13

申请人： Tadahiko Sugibayashi ,  Isao Naritake

发明人： Tadahiko Sugibayashi ,  Isao Naritake

IPC分类号： G11C11/401 ,  C21C5/40 ,  G11C7/06 ,  G11C7/18 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C7/065

摘要： A semiconductor memory device including a plurality of sub-bit lines, a sense amplifier provided in common to the plurality of sub-bit lines which receives a data signal from a first one of the plurality of sub-bit lines, a main-bit line operatively coupled to the sense amplifier to receive an output of the sense amplifier, and a data latch circuit provided to latch data appearing on the main-bit line. The device further comprises a circuit for transferring a data signal of a second one of the plurality of sub-bit lines to the sense amplifier when the data latch circuit is being accessed to read out data latched in the data latch circuit.

摘要翻译： 一种包括多个子位线的半导体存储器件，一种与从多个子位线中的第一位接收数据信号的多个子位线公共地提供的读出放大器，主位线 操作地耦合到读出放大器以接收读出放大器的输出，以及数据锁存电路，用于锁存出现在主位线上的数据。 该装置还包括一个电路，用于当数据锁存电路被访问时，将多个子位线中的第二个子位线的第二个数据信号传送到读出放大器，以读出锁存在数据锁存电路中的数据。

公开(公告)号：US5596542A

公开(公告)日：1997-01-21

申请号：US536189

申请日：1995-09-29

申请人： Tadahiko Sugibayashi ,  Satoshi Utsugi ,  Isao Naritake

发明人： Tadahiko Sugibayashi ,  Satoshi Utsugi ,  Isao Naritake

IPC分类号： H01L21/66 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C29/835 ,  G11C11/408 ,  G11C11/4087 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

摘要： In a semiconductor memory device including: a plurality of sub word lines, a plurality of sub word decoders each connected to one of the sub word lines, a plurality of pairs of main word lines each pair connected to a number of the sub word decoders, and a plurality of main word decoders each connected to one of the pairs of main word lines, each of the main word decoders sets voltages at a respective pair of the pairs of main word lines different from each other in a selection mode and sets the voltages at a respective pair of the pairs of main word lines the same as each other in a non-selection mode.

摘要翻译： 一种半导体存储器件，包括：多个子字线，多个子字解码器，每个子字解码器各自连接到一个子字线，多对主字线对，每对连接到多个子字解码器， 以及多个主字解码器，每个主字解码器连接到一对主字线中的每一个，每个主字解码器在选择模式下设置彼此不同的一对主字线对的电压，并将电压 在非选择模式下，相应的一对主字线彼此相同。

公开(公告)号：US5416368A

公开(公告)日：1995-05-16

申请号：US232407

申请日：1994-04-25

申请人： Tadahiko Sugibayashi

发明人： Tadahiko Sugibayashi

IPC分类号： H03K17/687 ,  G11C11/407 ,  G11C11/409 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948

CPC分类号： H03K19/018521 ,  G09G2310/0289

摘要： A level conversion output circuit includes two level conversion circuits for "high" and "low" logic signals, each of which includes a first CMOS inverter operating between an internal power supply of 3.3 V and ground, and a second CMOS inverter operating between an external power supply of 5 V and ground. One of the level conversion circuits is provided with an additional p-MOS transistor so that a 5.0 V voltage is applied to a gate of a p-MOS transistor of the second CMOS inverter from the external power supply through the additional p-MOS transistor, when the p-MOS transistor of the second CMOS inverter is controlled to be turned off.

摘要翻译： 电平转换输出电路包括用于“高”和“低”逻辑信号的两个电平转换电路，每个电平转换电路包括在3.3V的内部电源和地之间工作的第一CMOS反相器和在外部 电源电压为5 V，接地。 电平转换电路中的一个具有附加的p-MOS晶体管，使得通过附加的p-MOS晶体管从外部电源将5.0V电压施加到第二CMOS反相器的p-MOS晶体管的栅极， 当第二CMOS反相器的p-MOS晶体管被控制为截止时。

公开(公告)号：US5373477A

公开(公告)日：1994-12-13

申请号：US9974

申请日：1993-01-26

申请人： Tadahiko Sugibayashi

发明人： Tadahiko Sugibayashi

IPC分类号： G11C11/407 ,  G11C5/14

CPC分类号： G11C5/143 ,  G11C5/147

摘要： A dynamic random access memory device is equipped with an internal power supply system for selectively distributing a step-down power voltage to internal component circuits, and the internal power supply system comprises a feedback loop for regulating the step-down power voltage on an internal power supply line to a reference voltage, a voltage detecting circuit monitoring an internal power voltage line to see whether or not the step-down power voltage is decayed to a critical level for producing a gate control signal, and an auxiliary variable load transistor coupled between the external power supply line and the internal power supply line and responsive to the gate control signal for supplementing current to the internal power supply line, wherein the critical level is inversely proportional to the external power voltage while the external power voltage is higher than the reference voltage, thereby preventing the step-down power voltage from undesirable overshoot upon production of the gate control signal.

摘要翻译： 一种动态随机存取存储器件配备有用于选择性地将降压电源电压分配到内部组件电路的内部电源系统，并且内部电源系统包括用于调节内部功率上的降压功率电压的反馈回路 供给线到参考电压，电压检测电路监视内部电源电压线，以查看降压电源电压是否衰减到用于产生栅极控制信号的临界电平;以及辅助可变负载晶体管，其耦合在 外部电源线和内部电源线，并响应于栅极控制信号补充到内部电源线的电流，其中临界电平与外部电源电压成反比，而外部电源电压高于参考电压 从而在生产t时防止降压电源电压不受不良过冲 他门控制信号。

公开(公告)号：US5337270A

公开(公告)日：1994-08-09

申请号：US935162

申请日：1992-08-26

申请人： Koji Kawata ,  Tadahiko Sugibayashi

发明人： Koji Kawata ,  Tadahiko Sugibayashi

IPC分类号： G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/24

CPC分类号： G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

摘要： A DRAM according to the invention is provided with a memory cell array formed by arranging in the row and column directions one-transistor-one-capacitor type memory cells; bit lines, precharged at a prescribed timing, for performing the transfers of write-in/read-out data to and from the memory cells; a sense amplifier including a first transistor, whose drains are connected to the bit lines to bias the substrate to a prescribed potential, and a second transistor whose drains and sources are connected to the sources of the first transistor and a ground potential point, respectively, whose gates receive an activation control signal and whose substrate is biased to the same potential as the first transistor is, for amplifying the signals of said bit lines when activated; an intermediate potential generating circuit for supplying an intermediate potential which is substantially equal to 1/2 of the source potential to the opposite electrodes of said memories and to the bit lines; a power turn-on sensing circuit for generating a sensing signal which takes on an active level after the source potential reaches a prescribed level; and intermediate potential supply control means responsive to the sensing signal for controlling the supply of the intermediate potential to the bit lines.The current sources of said first and second transistors are cut off, power consumption is thereby saved and the occurrence of a latch-up phenomenon suppressed by suspending the supply of the intermediate potential to the bit lines during the period in which, immediately after the power is turned on, the substrate potential rises and the threshold values of the first and second transistors drop to keep these transistors in an ON state.

摘要翻译： 根据本发明的DRAM具有通过在行和列方向上布置单晶体管 - 单电容器型存储单元而形成的存储单元阵列; 位线，以规定的时间预充电，用于执行向存储器单元传送写入/读出数据; 包括第一晶体管的读出放大器，其漏极连接到位线以将衬底偏置到规定电位;以及第二晶体管，其漏极和源极分别连接到第一晶体管的源极和地电位点， 其门接收激活控制信号，并且其基板被偏置到与第一晶体管相同的电位，用于在激活时放大所述位线的信号; 中间电位产生电路，用于将基本上等于源极电位的1/2的中间电位提供给所述存储器的相对电极和位线; 电源接通感测电路，用于产生在所述电源电位达到规定电平之后呈现有效电平的感测信号; 以及中间电位供应控制装置，用于响应于感测信号，用于控制对位线的中间电位的供应。 所述第一和第二晶体管的电流源被切断，由此节省功率消耗，并且在电源紧接之后的时段期间通过暂停将中间电位供应给位线来抑制锁存现象的发生 导通时，衬底电位升高，并且第一和第二晶体管的阈值下降以保持这些晶体管处于导通状态。

公开(公告)号：US5289061A

公开(公告)日：1994-02-22

申请号：US937055

申请日：1992-08-26

申请人： Tadahiko Sugibayashi ,  Yasuji Koshikawa ,  Ryuji Yamamura

发明人： Tadahiko Sugibayashi ,  Yasuji Koshikawa ,  Ryuji Yamamura

IPC分类号： H03K19/0948 ,  G11C11/407 ,  G11C11/409 ,  H03K19/0185 ,  H03K5/00

CPC分类号： H03K19/018521

摘要： An output gate according to the present invention includes a CMOS gate composed of a P-MOS transistor connected at a source to an external power supply and a first N-MOS transistor connected at a source to ground, and a second N-MOS transistor connected between ground and the first N-MOS transistor by a source-drain path. The second N-MOS transistor is connected at a gate to an external power supply.

摘要翻译： 根据本发明的输出门包括由源极连接到外部电源的P-MOS晶体管和连接到源极的第一N-MOS晶体管构成的CMOS栅极和连接到第二N-MOS晶体管的第二N-MOS晶体管 通过源极 - 漏极路径在地和第一N-MOS晶体管之间。 第二N-MOS晶体管在栅极连接到外部电源。

公开(公告)号：US5287011A

公开(公告)日：1994-02-15

申请号：US912756

申请日：1992-07-13

申请人： Yasuji Koshikawa ,  Takahiro Hara ,  Tadahiko Sugibayashi

发明人： Yasuji Koshikawa ,  Takahiro Hara ,  Tadahiko Sugibayashi

IPC分类号： G11C11/401 ,  G11C11/407 ,  H03K17/14 ,  H03K17/22 ,  H03K3/01

CPC分类号： H03K17/22 ,  H03K17/145

摘要： A power-on detecting circuit produces a power-on signal upon power-on event for initializing internal component circuits, and comprises a timing generating unit for producing a timing signal when a power voltage level reaches a predetermined voltage level, a monitoring unit for producing an enable signal when a step-down power voltage level reaches a constant level, and a signal generating unit for producing the power-on signal in the concurrent presence of the enable signal and the timing signal, thereby guaranteeing the initialization of the internal component circuits.

摘要翻译： 上电检测电路在用于初始化内部组件电路的电源接通事件时产生通电信号，并且包括用于在电源电压达到预定电压电平时产生定时信号的定时产生单元，用于产生 当降压功率电压电平达到恒定电平时的使能信号，以及用于在同时存在使能信号和定时信号时产生通电信号的信号产生单元，从而保证内部组件电路的初始化 。