公开(公告)号：US20220271047A1

公开(公告)日：2022-08-25

申请号：US17184892

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Song-Fu Liao ,  Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L27/11507 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.

公开(公告)号：US20220271046A1

公开(公告)日：2022-08-25

申请号：US17184856

申请日：2021-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

公开(公告)号：US11355516B2

公开(公告)日：2022-06-07

申请号：US17018232

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3213

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

公开(公告)号：US11355496B2

公开(公告)日：2022-06-07

申请号：US17086628

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Chung-Te Lin

IPC: H01L27/108

Abstract: A semiconductor device comprises a semiconductor substrate, and a pair of metal gates extends upwards from the semiconductor substrate. First and second channel regions are disposed between inner sidewalls of the pair of metal gates. First and second drain regions are disposed between the inner sidewalls of the pair of metal gates and are disposed directly over the first and second channel regions, respectively. First and second source regions are disposed between the inner sidewalls of the pair of metal gates directly below the first and second channel regions, respectively. A capacitor dielectric structure is disposed below the first and second source regions. A bottom capacitor electrode is disposed below the capacitor dielectric. The capacitor dielectric structure separates the first and second drain regions from the bottom capacitor electrode.

公开(公告)号：US20220139935A1

公开(公告)日：2022-05-05

申请号：US17166078

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. This ferroelectric material may be of the composition HFxZr1-xO2. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). A ferroelectric layer formed with chlorine-free precursors has no chlorine residue. The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

公开(公告)号：US20220037361A1

公开(公告)日：2022-02-03

申请号：US17112606

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/522 ,  H01L27/1159

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US11170152B2

公开(公告)日：2021-11-09

申请号：US16912229

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung Chen ,  Chung-Te Lin ,  Fong-Yuan Chang ,  Ho Che Yu ,  Li-Chun Tien

IPC: G06F7/50 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/394

Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.

公开(公告)号：US11088067B2

公开(公告)日：2021-08-10

申请号：US16913697

申请日：2020-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Pin-Dai Sue

IPC: H01L23/522 ,  H01L27/118 ,  H01L27/02

Abstract: A device includes gates and a first conductive segment. A first distance is present between a first gate of the gates and the first conductive segment. A second distance is present between a second gate of the gates and the first conductive segment. The first distance is greater than the second distance.

公开(公告)号：US10964888B2

公开(公告)日：2021-03-30

申请号：US16840100

申请日：2020-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pin-Ren Dai ,  Chung-Ju Lee ,  Chung-Te Lin ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Tai-Yen Peng ,  Chien-Min Lee ,  Wei-Hao Liao

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

公开(公告)号：US20210082960A1

公开(公告)日：2021-03-18

申请号：US17103532

申请日：2020-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chun-Chen Chen ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Chung-Te Lin ,  Jerry Chang Jui Kao ,  Sheng-Hsiung Chen ,  Chin-Chou Liu

IPC: H01L27/118 ,  G06F30/398

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.