公开(公告)号：US20200043804A1

公开(公告)日：2020-02-06

申请号：US16599912

申请日：2019-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L21/311 ,  H01L27/092

Abstract: A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure and over the first layer. The gate layer is patterned into a gate stack that wraps around the fin structure. A second layer is formed over the first layer and over the gate stack. A first etching process is performed to remove portions of the second layer formed over the fin structure, the first layer serves as an etching-stop layer during the first etching process. A second etching process is performed to remove portions of the first layer to expose a portion of the fin structure. A removal of the portions of the first layer does not substantially affect the second layer. A source/drain region is epitaxially grown on the exposed portion of the fin structure.

公开(公告)号：US20200006158A1

公开(公告)日：2020-01-02

申请号：US16218330

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Yi-Hsiu Liu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.

公开(公告)号：US10453753B2

公开(公告)日：2019-10-22

申请号：US15966186

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L21/311 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161

Abstract: A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure and over the first layer. The gate layer is patterned into a gate stack that wraps around the fin structure. A second layer is formed over the first layer and over the gate stack. A first etching process is performed to remove portions of the second layer formed over the fin structure, the first layer serves as an etching-stop layer during the first etching process. A second etching process is performed to remove portions of the first layer to expose a portion of the fin structure. A removal of the portions of the first layer does not substantially affect the second layer. A source/drain region is epitaxially grown on the exposed portion of the fin structure.

公开(公告)号：US20190252527A1

公开(公告)日：2019-08-15

申请号：US16396961

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/165 ,  H01L21/225

CPC classification number: H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165 ,  H01L29/66818

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US20190139836A1

公开(公告)日：2019-05-09

申请号：US15806603

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/0274 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/7848

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.

公开(公告)号：US20190074225A1

公开(公告)日：2019-03-07

申请号：US16181847

申请日：2018-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Chia-Ta Yu ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method includes providing a device structure having a substrate, an isolation structure over the substrate, and two fins extending from the substrate and through the isolation structure, each fin having two source/drain (S/D) regions and a channel region; depositing a first dielectric layer over top and sidewall surfaces of the fins and over the isolation structure; forming a gate stack over the first dielectric layer and engaging each fin at the respective channel region; treating surfaces of the gate stack and the first dielectric layer such that the surfaces of the gate stack are more attachable to a second dielectric layer than the surfaces of the first dielectric layer are; after the treating of the surfaces, depositing the second dielectric layer; and etching the first dielectric layer to expose the S/D regions of the fins.

公开(公告)号：US10217815B1

公开(公告)日：2019-02-26

申请号：US15796968

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Feng-Cheng Yang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/78

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

公开(公告)号：US10158017B2

公开(公告)日：2018-12-18

申请号：US15684088

申请日：2017-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/78 ,  H01L21/84 ,  H01L27/11 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, first gate structures and second gate structures over the substrate, third epitaxial semiconductor features proximate the first gate structures, and fourth epitaxial semiconductor features proximate the second gate structures. The first gate structures have a greater pitch than the second gate structures. The third and fourth epitaxial semiconductor features are at least partially embedded in the substrate. A first proximity of the third epitaxial semiconductor features to the respective first gate structures is smaller than a second proximity of the fourth epitaxial semiconductor features to the respective second gate structures. In an embodiment, a first depth of the third epitaxial semiconductor features embedded into the substrate is greater than a second depth of the fourth epitaxial semiconductor features embedded into the substrate.

公开(公告)号：US10068992B2

公开(公告)日：2018-09-04

申请号：US15590301

申请日：2017-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung Lo ,  Tzu-Hsiang Hsu ,  Chia-Jung Hsu ,  Feng-Cheng Yang ,  Teng-Chun Tsai ,  Ying-Ho Chen

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8238

Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.

公开(公告)号：US09780214B2

公开(公告)日：2017-10-03

申请号：US14579708

申请日：2014-12-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gin-Chen Huang ,  Tzu-Hsiang Hsu ,  Chia-Jung Hsu ,  Feng-Cheng Yang ,  Teng-Chun Tsai

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/12 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L29/12 ,  H01L29/165 ,  H01L29/511 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.