公开(公告)号：US11830928B2

公开(公告)日：2023-11-28

申请号：US17458087

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L29/66553 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7853

Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.

公开(公告)号：US20230369047A1

公开(公告)日：2023-11-16

申请号：US18361878

申请日：2023-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Ya-Wen Yeh ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Ru-Gun Liu ,  Kuei-Shun Chen

IPC: H01L21/027 ,  G03F7/09 ,  H01L21/311 ,  H01L21/033 ,  G03F7/20 ,  H01L21/306 ,  G03F7/11

CPC classification number: H01L21/0273 ,  G03F7/09 ,  H01L21/0337 ,  H01L21/311 ,  G03F7/11 ,  G03F7/20 ,  H01L21/0274 ,  H01L21/306

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

公开(公告)号：US11728221B2

公开(公告)日：2023-08-15

申请号：US17201342

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lun Chen ,  Chao-Hsien Huang ,  Li-Te Lin ,  Chun-Hsiung Lin

IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/823864 ,  H01L29/515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

公开(公告)号：US20230246089A1

公开(公告)日：2023-08-03

申请号：US18298095

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823431 ,  H01L29/6656 ,  H01L21/823842 ,  H01L29/4966

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US11707803B2

公开(公告)日：2023-07-25

申请号：US17832832

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Li-Te Lin ,  Pinyen Lin

IPC: B23K26/348 ,  H01L21/3115 ,  B23K26/067 ,  B23K26/06 ,  H01L21/311

CPC classification number: B23K26/348 ,  B23K26/0643 ,  B23K26/0676 ,  H01L21/31116 ,  H01L21/31155

Abstract: A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.

公开(公告)号：US11652152B2

公开(公告)日：2023-05-16

申请号：US17238968

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Ming-Huan Tsai ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/08

CPC classification number: H01L29/4983 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

公开(公告)号：US20230118700A1

公开(公告)日：2023-04-20

申请号：US18066354

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

Abstract: A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.

公开(公告)号：US20230050650A1

公开(公告)日：2023-02-16

申请号：US17402030

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hao CHANG ,  Po-Chin Chang ,  Pinyen Lin ,  Li-Te Lin

IPC: H01J37/32 ,  H01L21/263 ,  H01L21/687

Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.

公开(公告)号：US20230027676A1

公开(公告)日：2023-01-26

申请号：US17689644

申请日：2022-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Chien Kuang ,  Wei-Lun Chen ,  Tze-Chung Lin ,  Li-Te Lin

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306

Abstract: The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F2) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.

公开(公告)号：US11545397B2

公开(公告)日：2023-01-03

申请号：US17143698

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Tzer-Min Shen ,  Fu-Ting Yen ,  Gary Chan ,  Keng-Chu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3065

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.