-
公开(公告)号：US06381275B1
公开(公告)日：2002-04-30
申请号：US08759834
申请日：1996-12-04
IPC分类号： H04N718
CPC分类号： H04N19/00 , H04N19/23 , H04N19/423 , H04N19/503 , H04N19/577 , H04N19/587 , H04N19/59 , H04N19/61
摘要： An image coding apparatus which includes a frame memory selecting unit (35) for selecting, in response to a selection signal, an image to be continuously stored in a plurality of frame memories (9, 10) as a background image and storing the background image into the plurality of frame memories (9, 10), and a background motion compensating unit (14, 39) for performing motion compensating prediction corresponding to an input image based on the background image to generate a predicted image based on the motion compensating prediction, and an image decoding apparatus corresponding to the image coding apparatus.
摘要翻译： 一种图像编码装置，包括：帧存储器选择单元，用于响应于选择信号选择要连续存储在多个帧存储器（9,10）中的图像作为背景图像并存储背景图像 进入多个帧存储器（9,10）和背景运动补偿单元（14,39），用于基于背景图像执行与输入图像相对应的运动补偿预测，以基于运动补偿预测生成预测图像， 以及与图像编码装置对应的图像解码装置。
-
92.发明授权Image coded data re-encoding apparatus without once decoding the original image coded data 失效图像编码数据重新编码装置，一次解码原始图像编码数据公开(公告)号：US06246438B1
公开(公告)日：2001-06-12
申请号：US09351283
申请日：1999-07-12
IPC分类号： H04N712
CPC分类号： H04N19/40 , H04N19/124 , H04N19/126 , H04N19/46 , H04N19/60
摘要： An image coded data re-encoding apparatus (30) which generates in an image coded data analyzer (310) coded data after signal processing (221) by performing a first digital signal processing on first image coded data (220), supplies an image coded data synthesizer (320) with the coded data after signal processing (221) and multiple signals (222) associated with the first image coded data, and generates in the image coded data synthesizer (320) a second image coded data (240) by performing on the coded data after signal processing (221) a second digital signal processing based on multiple signals (222). The second image coded data is generated without once decoding the first image coded data. This makes it possible to prevent degradation in image quality, delay involved in the transform and an increase of the device size.
摘要翻译： 一种在图像编码数据分析器（310）中通过对第一图像编码数据（220）执行第一数字信号处理在信号处理（221）之后生成编码数据的图像编码数据重新编码装置（30），提供图像编码数据 数据合成器（320）与信号处理后的编码数据（221）和与第一图像编码数据相关联的多个信号（222），并且通过执行第二图像编码数据（240）在图像编码数据合成器（320）中生成第二图像编码数据 对信号处理后的编码数据（221）进行基于多个信号的第二数字信号处理（222）。 生成第二图像编码数据而不对第一图像编码数据进行一次解码。 这使得可以防止图像质量的降低，变形中涉及的延迟和装置尺寸的增加。
-
公开(公告)号：US06208689B1
公开(公告)日：2001-03-27
申请号：US08806668
申请日：1997-02-26
IPC分类号： H04B166
CPC分类号： H04N19/577 , H04N19/115 , H04N19/126 , H04N19/14 , H04N19/15 , H04N19/159 , H04N19/172 , H04N19/177 , H04N19/423 , H04N19/428 , H04N19/61
摘要： A method and apparatus of digital image decoding is provided for reducing compression-related deterioration of an image to a minimum with a reduced storage capacity. The digital image decoding apparatus is equipped with a compression rate judging section for judging an optimal rate of compression for effecting the least deterioration to the image based upon the size of image in connection with the storage capacity of a frame memory. A compressing section compresses decoded data based upon the optimal rate of compression and sends the compressed data to a predictive/display frame memory for storage. An expanding A section expands the compressed data based upon the optimal rate of compression and sends the expanded data to a decoding section when the expanded data is required. An expanding B section reads out the compressed data of a display frame from the predictive/display frame memory and expands the compressed data based upon the optimal rate of compression and sends the expanded data to a display unit for display.
摘要翻译： 提供一种数字图像解码的方法和装置，用于以降低的存储容量将图像的压缩相关劣化降至最低。 数字图像解码装置配备有压缩率判定部，其根据与帧存储器的存储容量相关联的图像的大小来判断压缩的最佳速率，以实现图像的劣化。 压缩部分基于最佳压缩率压缩解码数据，并将压缩数据发送到预测/显示帧存储器以进行存储。 扩展的A部分根据最佳压缩速率扩展压缩数据，并在扩展数据需要时将扩展数据发送到解码部分。 扩展B部分从预测/显示帧存储器中读出显示帧的压缩数据，并根据最佳压缩率扩展压缩数据，并将扩展数据发送到显示单元进行显示。
-
公开(公告)号：US06188794B1
公开(公告)日：2001-02-13
申请号：US09315038
申请日：1999-05-20
IPC分类号： G06K938
CPC分类号： H04N19/577 , H04N19/105 , H04N19/112 , H04N19/119 , H04N19/124 , H04N19/132 , H04N19/137 , H04N19/14 , H04N19/152 , H04N19/16 , H04N19/172 , H04N19/176 , H04N19/61
摘要： An adaptive blocking coding system selects an effective blocking of an input image signal to be encoded in accordance with the correlation between fields, even if motion is detected between the fields. The blocking patterns include an individual field blocking, a non-interlace blocking, a split blocking and an inverted split blocking. Further, the coding system searches for motion from both odd and even fields of a frame for producing a motion compensated prediction signal in order to provide high-efficient coding.
摘要翻译： 即使在场之间检测到运动，自适应阻塞编码系统根据场之间的相关性选择要编码的输入图像信号的有效阻塞。 阻塞模式包括单独的场阻塞，非交错阻塞，分割阻塞和反向拆分阻塞。 此外，编码系统搜索用于产生运动补偿预测信号的帧的奇数和偶数场的运动，以便提供高效编码。
-
公开(公告)号：US6002439A
公开(公告)日：1999-12-14
申请号：US320726
申请日：1999-05-27
IPC分类号： H04N19/60 , G06T9/00 , H04N11/04 , H04N19/00 , H04N19/119 , H04N19/124 , H04N19/129 , H04N19/132 , H04N19/136 , H04N19/176 , H04N19/196 , H04N19/85 , H04N19/91 , H04N7/32
CPC分类号： H04N19/577 , H04N19/105 , H04N19/112 , H04N19/119 , H04N19/124 , H04N19/132 , H04N19/137 , H04N19/14 , H04N19/152 , H04N19/16 , H04N19/172 , H04N19/176 , H04N19/61
摘要： An adaptive blocking coding system selects an effective blocking of an input image signal to be encoded in accordance with the correlation between fields, even if motion is detected between the fields. The blocking patterns include an individual field blocking, a non-interlace blocking, a split blocking and an inverted split blocking. Further, the coding system searches for motion from both odd and even fields of a frame for producing a motion.,compensated prediction signal in order to provide high-efficient coding.
摘要翻译： 即使在场之间检测到运动，自适应阻塞编码系统根据场之间的相关性选择要编码的输入图像信号的有效阻塞。 阻塞模式包括单独的场阻塞，非交错阻塞，分割阻塞和反向拆分阻塞。 此外，编码系统搜索用于产生运动的帧的奇数和偶数场的运动，补偿预测信号以提供高效编码。
-
96.发明授权Method and apparatus for filtering and coding images based on characteristics of an input image signal 失效基于输入图像信号的特性对图像进行滤波和编码的方法和装置
公开(公告)号：US5543848A
公开(公告)日：1996-08-06
申请号：US355987
申请日：1994-12-14
IPC分类号： H04N19/50 , G06T9/00 , H04N19/107 , H04N19/117 , H04N19/126 , H04N19/132 , H04N19/136 , H04N19/137 , H04N19/14 , H04N19/152 , H04N19/189 , H04N19/196 , H04N19/423 , H04N19/46 , H04N19/503 , H04N19/51 , H04N19/593 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/80 , H04N19/82 , H04N19/85 , H04N7/32
CPC分类号： H04N19/86 , H04N19/107 , H04N19/112 , H04N19/117 , H04N19/14 , H04N19/149 , H04N19/172 , H04N19/503 , H04N19/527 , H04N19/61 , H04N19/80 , H04N19/82 , H04N19/146
摘要： An interframe coding system which eliminates higher frequency components contained in an image signal effectively and adaptively with an adaptive filter provided in a coding loop. The adaptive filter eliminates the higher frequency components with the optimal filtering intensity for an image signal specified with a filtering coefficient which is decided by a filter controller. The filtering coefficient is decided by normalization of the difference between an input image signal and a predictive signal from a frame memory by the "Activity" of the input image signal or the predictive signal. The "Activity" can be based upon the sum of the absolute or squared difference values based upon the mean value of luminance intensity of pixels of the image signal.
摘要翻译： 一种帧间编码系统，其利用编码环路中提供的自适应滤波器有效地自适应地消除图像信号中包含的较高频率分量。 自适应滤波器消除了由滤波器控制器决定的滤波系数指定的图像信号的最佳滤波强度的较高频率分量。 通过输入图像信号或预测信号的“活动”将来自帧存储器的输入图像信号和预测信号之间的差异归一化来确定滤波系数。 “活动”可以基于基于图像信号的像素的亮度强度的平均值的绝对值或平方差值的总和。
-
公开(公告)号：USRE34850E
公开(公告)日：1995-02-07
申请号：US803457
申请日：1991-12-06
IPC分类号： G06F15/16 , G06F9/32 , G06F13/28 , G06F15/167 , G06F15/78 , G06F15/80 , G06F17/10 , G06T1/00 , H03H17/02 , G06F13/14
CPC分类号： G06F13/28 , G06F15/7857
摘要： A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.
摘要翻译： 数字信号处理器包括总线结构，包括程序总线，数据总线和数据输入/输出总线，程序存储器，程序控制器，由用于存储块数据的多个2-端口存储器构成的内部数据存储器， 算术运算器，用于在算术运算器的内部操作中并行地实现内部数据存储器和外部数据存储器之间的块数据输入/输出的DMA控制器，用于同时产生用于内部操作和DMA传输的地址的地址生成器 与内部操作并行的并行数据输入/输出端口，用于独立于输入/输出操作和异步方式实现与外部设备的并行数据通信。 处理器执行复杂的自适应处理算法，例如高速和高吞吐量的图像信号处理。
-
公开(公告)号：USRE34562E
公开(公告)日：1994-03-15
申请号：US761501
申请日：1991-09-18
申请人： Tokumichi Murakami , Masami Nishida , Atsushi Ito
发明人： Tokumichi Murakami , Masami Nishida , Atsushi Ito
CPC分类号： H03M7/3082 , G06T9/008 , H04N19/94
摘要： An amplitude-adaptive vector quantization system intended for efficient signal coding and decoding. A mean value separation circuit (2) separates the mean value from an input signal which has been divided into blocks, and a tree-search vector quantizer (6) implements tree-search inner product vector quantization so that index information is truncated depending on the detected vector amplitude, thereby reducing the volume of information for transmission.
摘要翻译： PCT No.PCT / JP87 / 00793 Sec。 371日期：1988年5月26日 102（e）日期1988年5月26日PCT提交1987年10月16日PCT公布。 出版物WO88 / 02975 日期1988年4月21日。一种用于高效信号编码和解码的幅度自适应矢量量化系统。 平均值分离电路（2）将已经被划分成块的输入信号的平均值分离，并且树搜索矢量量化器（6）实现树搜索内积矢量量化，使得索引信息根据 检测到矢量幅度，从而减少用于传输的信息量。
-
公开(公告)号：US5206940A
公开(公告)日：1993-04-27
申请号：US750512
申请日：1991-08-27
申请人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
发明人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
CPC分类号： G06F7/575 , G06F13/28 , G06F15/7832 , G06F15/7842 , G06F15/786 , G06F9/30058 , G06F9/30094 , G06F9/355 , G06F9/3877 , G06F9/3885 , G06F2207/3884
摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段
-
100.发明授权
公开(公告)号：US5161247A
公开(公告)日：1992-11-03
申请号：US379274
申请日：1989-07-13
CPC分类号： G06T7/202 , G06T7/2013 , G06T7/2026 , H04N19/43 , H04N19/433 , H04N19/51 , H04N19/533 , H04N5/145 , G06T2200/28 , G06T2207/10016
摘要： The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reducing a required amount of calculations when an amount of distortion between a last frame block and a current frame block; in processing a direct memory access at a higher efficiency; in processing a subdivided data calculation at a higher speed; in processing a branch instruction occurring in the pipeline process at a higher efficiency; and in processing an interruption occurring in a repeat process operation at greater convenience, and furthermore in reducing a required amount of calculations through minimum distortion searching processes hierarchized.
摘要翻译： 本发明改进了数字信号处理器，更具体地，涉及当在最后帧块和当前帧块之间的失真量时减少计算所需量的运动补偿的计算方法; 在更高效率地处理直接存储器访问; 在更高速度处理细分数据计算; 在管理过程中以更高的效率处理分支指令; 并且在更加方便的情况下处理在重复处理操作中发生的中断，并且还通过层级化的最小失真搜索处理来减少所需的计算量。
-
-
-
-
-
-
-
-
-
搜索结果
190 条记录 (耗时 0.049 秒)
