公开(公告)号：US20090230555A1

公开(公告)日：2009-09-17

申请号：US12049698

申请日：2008-03-17

Applicant: Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

Inventor： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53223 ,  H01L23/5329 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

Abstract translation: 在半导体衬底上形成包含埋在电介质材料层中的底层W通孔的底层互连层。 一种金属层堆叠，包括从底部到顶部的低氧反应性金属层，底部过渡金属层，底部过渡金属氮化物层，铝 - 铜层，任选的顶部过渡金属层和顶部过渡层 金属氮化物层。 金属层堆叠被光刻图案化以形成至少一个构成金属互连结构的铝基金属线。 低氧反应性金属层由于通过低氧反应性金属层防止了底部过渡金属层和电介质材料层之间的化合物的形成，因此提高了至少一种铝基金属线的电迁移率 不与介电材料层相互作用。

公开(公告)号：US20090183131A1

公开(公告)日：2009-07-16

申请号：US12050990

申请日：2008-03-19

Applicant: Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

Inventor： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

IPC: G06F17/50

CPC classification number: H01L23/345 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

Abstract translation: 公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。 修理方案在每个设备上使用加热元件。 加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。 具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。 加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

公开(公告)号：US07511378B2

公开(公告)日：2009-03-31

申请号：US11442911

申请日：2006-05-30

Applicant: Jason P. Gill ,  David L. Harmon ,  Deborah M. Massey ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Junichi Furukawa

Inventor： Jason P. Gill ,  David L. Harmon ,  Deborah M. Massey ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Junichi Furukawa

IPC: H01L23/48

CPC classification number: G06F17/5077 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H05K1/0201 ,  H05K3/0005 ,  H01L2924/00

Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

Abstract translation: 具有布线的电子结构以及用于限制布线中的温度梯度的结构设计的相关方法。 该电子结构包括具有包括不物理接触的第一和第二线的层的衬底。 由于焦耳加热相对于第一和第二导线中的电流密度，第一和第二导线适于处于升高的温度。 第一导线通过存在于层之外的导电和导热结构电耦合到第二导线。 第二导线的宽度被调整为将第一导线中的温度梯度限制在低于预定足够小的阈值，以便基本上减轻第一线中的电迁移的不利影响。

公开(公告)号：US07470613B2

公开(公告)日：2008-12-30

申请号：US11619748

申请日：2007-01-04

Applicant: Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

Inventor： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

IPC: H01L21/4763

CPC classification number: H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

Abstract translation: 一种用于形成互连结构的方法，所述互连结构包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下导电衬垫在侧面和底部 的下层电线; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

公开(公告)号：US20080297188A1

公开(公告)日：2008-12-04

申请号：US11755827

申请日：2007-05-31

Applicant: Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

Inventor： Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  G01R31/2875 ,  G01R31/2879

Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.

Abstract translation: 公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。 该方法的一个实施例包括：对线路施加恒定电流IS; 并在施加恒定电流IS的同时对线进行应力测试，使得恒定电流IS不会由于电迁移的开始而被电阻变化所改变。

公开(公告)号：US07445966B2

公开(公告)日：2008-11-04

申请号：US11160468

申请日：2005-06-24

Applicant: John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Timothy D. Sullivan ,  Steven H. Voldman

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Timothy D. Sullivan ,  Steven H. Voldman

IPC: H01L23/60

CPC classification number: H01L27/0248 ,  Y10S438/926

Abstract: A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

Abstract translation: 一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。 该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

公开(公告)号：US20080231312A1

公开(公告)日：2008-09-25

申请号：US12154304

申请日：2008-05-22

Applicant: Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

Inventor： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

Abstract translation: 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

公开(公告)号：US06992390B2

公开(公告)日：2006-01-31

申请号：US10702651

申请日：2003-11-07

Applicant: Daniel C. Edelstein ,  Baozhen Li ,  Timothy D. Sullivan

Inventor： Daniel C. Edelstein ,  Baozhen Li ,  Timothy D. Sullivan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76846 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection structure for semiconductor integrated circuits is disclosed. The interconnection structure comprises a redundant layer, and at least one adhesion/diffusion barrier layer. The redundant layer comprises a metal or metal alloy selected from Ta, Mo, W, Be, Cr, Co, Ir, Ni, Nb, Os, Pd, Pt, Rb, Rh, Ru, and Th.

Abstract translation: 公开了一种用于半导体集成电路的互连结构。 互连结构包括冗余层和至少一个粘附/扩散阻挡层。 冗余层包括选自Ta，Mo，W，Be，Cr，Co，Ir，Ni，Nb，Os，Pd，Pt，Rb，Rh，Ru和Th中的金属或金属合金。

公开(公告)号：US06798066B1

公开(公告)日：2004-09-28

申请号：US10249910

申请日：2003-05-16

Applicant: William T. Motsiff ,  Timothy D. Sullivan ,  Jean E. Wynne ,  Sally J. Yankee

Inventor： William T. Motsiff ,  Timothy D. Sullivan ,  Jean E. Wynne ,  Sally J. Yankee

IPC: H01L2348

CPC classification number: H01L23/60 ,  H01L23/36 ,  H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to dissipating heat from an interconnect formed in a low thermal conductivity dielectric in an integrated circuit apparatus. The integrated circuit apparatus includes integrated circuit devices interconnected by conductive interconnection metallurgy and input/output pads subject to electrostatic discharge events. At least one latent heat of transformation absorber is associated with at least one of the input/output pads for preventing the energy generated by an electrostatic discharge event from damaging the conductive interconnection metallurgy.

Abstract translation: 本发明涉及从形成在集成电路装置中的低导热电介质中的互连件散热。 集成电路装置包括通过导电互连冶金互连的集成电路装置和经受静电放电事件的输入/输出垫。 至少一个变换吸收器的潜热与至少一个输入/输出焊盘相关联，用于防止由静电放电事件产生的能量损坏导电互连冶金。

公开(公告)号：US06639242B1

公开(公告)日：2003-10-28

申请号：US10064303

申请日：2002-07-01

Applicant: Fen Chen ,  Timothy D. Sullivan

Inventor： Fen Chen ,  Timothy D. Sullivan

IPC: H01L2906

CPC classification number: H01L23/38 ,  H01L2924/0002 ,  Y10S257/93 ,  H01L2924/00

Abstract: A method and structure for a semiconductor structure that includes a substrate having at least one integrated circuit heat generating structure is disclosed. The invention has at least one integrated circuit cooling device on the substrate adjacent the heat generating structure. The cooling device is adapted to remove heat from the heat generating structure. The cooling device includes a cold region and a hot region. The cold region is positioned adjacent the heat generating structure. The cooling device has one of a silicon germanium super lattice structure. The cooling device also has a plurality of cooling devices that surround the heat generating structure. The cooling device includes a thermoelectric cooler.

Abstract translation: 公开了一种包括具有至少一个集成电路发热结构的基板的半导体结构的方法和结构。 本发明在与发热结构相邻的衬底上具有至少一个集成电路冷却装置。 冷却装置适于从发热结构中去除热量。 冷却装置包括冷区域和热区域。 冷区域位于发热结构附近。 冷却装置具有硅锗超晶格结构之一。 冷却装置还具有围绕发热结构的多个冷却装置。 冷却装置包括热电冷却器。