公开(公告)号：US08144498B2

公开(公告)日：2012-03-27

申请号：US12114667

申请日：2008-05-02

Applicant: Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

Inventor： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

IPC: G11C11/00

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

公开(公告)号：US08097878B2

公开(公告)日：2012-01-17

申请号：US11714326

申请日：2007-03-05

Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

IPC: H01L29/12 ,  H01L29/02

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US08049305B1

公开(公告)日：2011-11-01

申请号：US12580196

申请日：2009-10-15

Applicant: Michael Miller ,  Prashant Phatak ,  Tony Chiang

Inventor： Michael Miller ,  Prashant Phatak ,  Tony Chiang

IPC: H01L29/10

CPC classification number: H01L45/1233 ,  H01L23/5228 ,  H01L23/525 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode.

Abstract translation: 描述了使用应力工程的电阻变化存储器件，包括第一层，包括第一导电电极，第一层上方的第二层，包括电阻式开关元件，第二层上方的第三层包括第二导电电极， 在加热存储元件时在第一层和第二层之间的第一界面处在开关元件中产生第一应力，并且其中在第二层和第三层之间的第二界面处在开关元件中产生第二应力 加热。 等于第一应力和第二应力之间的差的应力梯度具有大于50MPa的绝对值，并且存储元件的复位电压具有相对于具有与应力梯度相反的符号的公共电位的极性， 应用于第一导电电极。

公开(公告)号：US07989343B2

公开(公告)日：2011-08-02

申请号：US12802701

申请日：2010-06-11

Applicant: Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

Inventor： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

Abstract: We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of each of the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. The method also comprises depositing a second portion of the metal seed layer while redistributing at least a portion of the bottom coverage material to the sidewalls of each recessed device feature, to provide a uniform seed layer coverage over the interior surface of the recessed device features.

Abstract translation: 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括在晶片衬底上沉积铜晶种层的第一部分，而不会在多个凹陷元件特征中的每一个的开口上过多地累积，同时获得底部覆盖而无需基本上溅射底面。 该方法还包括沉积金属种子层的第二部分，同时将底部覆盖材料的至少一部分重新分配到每个凹陷装置特征的侧壁，以在凹陷装置特征的内表面上提供均匀的种子层覆盖。

公开(公告)号：US20110014359A1

公开(公告)日：2011-01-20

申请号：US12921776

申请日：2009-04-17

Applicant: Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

Inventor： Imran Hashim ,  Indranil De ,  Tony Chiang ,  Edward Haywood ,  Hanhong Chen ,  Nobi Fuchigami ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: B05D5/12

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）具有高介电常数和低泄漏特性的方法，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US07824935B2

公开(公告)日：2010-11-02

申请号：US12167118

申请日：2008-07-02

Applicant: Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

Inventor： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

IPC: H01L21/00

CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

公开(公告)号：US20100258782A1

公开(公告)日：2010-10-14

申请号：US12705474

申请日：2010-02-12

Applicant: Ronald John Kuse ,  Imran Hashim ,  Tony Chiang

Inventor： Ronald John Kuse ,  Imran Hashim ,  Tony Chiang

IPC: H01L45/00 ,  H01L21/02

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1641

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract translation: 描述了具有改进的开关特性的电阻式开关存储元件，包括具有第一电极和第二电极的存储元件，第一电极和第二电极之间的开关层，包括氧化铪并具有第一厚度，以及耦合层， 所述开关层和所述第二电极，所述耦合层包括包含金属钛并且具有小于所述第一厚度的25％的第二厚度的材料。

公开(公告)号：US20100258781A1

公开(公告)日：2010-10-14

申请号：US12608934

申请日：2009-10-29

Applicant: Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

Inventor： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

IPC: H01L47/00

CPC classification number: H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

Abstract translation: 描述了包括掺杂硅电极的电阻式开关存储元件，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特之间 eV），第一电极和第二电极之间的金属氧化物层，金属氧化物层使用体积介导的开关进行开关，并且具有大于4eV的带隙，并且存储元件从低电阻状态切换到高电阻 状态，反之亦然。

公开(公告)号：US20100243983A1

公开(公告)日：2010-09-30

申请号：US12610131

申请日：2009-10-30

Applicant: Tony Chiang ,  Michael Miller ,  Prashant Phatak

Inventor： Tony Chiang ,  Michael Miller ,  Prashant Phatak

IPC: H01L47/00 ,  H01L21/16

CPC classification number: H01L45/122 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/56 ,  H01L21/265 ,  H01L21/322 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1675

Abstract: Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions.

Abstract translation: 描述了用于电阻存储器的受控局部缺陷路径，包括用于形成受控局部缺陷路径的方法，包括形成在第一电极上形成金属氧化物层的第一电极，掩蔽金属氧化物以产生暴露区域和隐藏区域 金属氧化物，并且改变金属氧化物的暴露区域以在暴露区域下方产生局部缺陷路径。

公开(公告)号：US20090026433A1

公开(公告)日：2009-01-29

申请号：US12179532

申请日：2008-07-24

Applicant: Tony Chiang

Inventor： Tony Chiang

IPC: H01L47/00

CPC classification number: H01L45/146 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79

Abstract: Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.

Abstract translation: 提供多个非易失性存储器元件。 多个非易失性存储器元件包含多个层。 每个层可以基于不同的双稳态材料。 双稳态材料可以是电阻式开关材料，例如电阻式开关金属氧化物。 可选导体层和电流导向元件可以与双稳电阻开关金属氧化物层串联连接。