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公开(公告)号：US20120012979A1
公开(公告)日：2012-01-19
申请号：US12837121
申请日：2010-07-15
CPC分类号： H01L28/65 , H01L21/3105 , H01L21/31111 , H01L21/3212 , H01L28/88
摘要： An improved semiconductor capacitor and method of fabrication is disclosed. A nitride stack, comprising alternating sublayers of slow-etch and fast-etch nitride is deposited on a substrate. The nitride stack is etched via an anisotropic etch technique such as reactive ion etch. A wet etch then etches the nitride stack, forming a corrugated shape. The corrugated shape increases surface area, and hence increases the capacitance of the capacitor.
摘要翻译： 公开了一种改进的半导体电容器和制造方法。 包括交替的缓慢蚀刻和快速蚀刻氮化物的子层的氮化物堆叠沉积在衬底上。 通过诸如反应离子蚀刻的各向异性蚀刻技术蚀刻氮化物层。 湿蚀刻然后蚀刻氮化物叠层，形成波纹形状。 波纹形状增加了表面积，因此增加了电容器的电容。
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公开(公告)号：US06228706B1
公开(公告)日：2001-05-08
申请号：US09384298
申请日：1999-08-26
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a method of manufacturing the same is provided.
摘要翻译： 一种记忆单元，包括具有顶表面的基底; 电容器垂直延伸到基板中，用于存储表示基准的电压，所述电容器占据几何形状的水平面积; 晶体管，形成在电容器上方并且占据基本上等于几何形状水平面积的水平面积，并且具有垂直器件深度，用于响应于控制信号与电容器建立电连接，用于读取和写入 所述电容器，其中所述晶体管包括形成在所述水平装置区域的周边附近并具有大约等于垂直装置深度的垂直深度的栅极; 栅极内表面上的氧化物层; 形成在所述氧化物层内部的导电体，所述导电体具有顶表面和底表面以及垂直深度近似等于垂直装置深度; 并且在顶部和底部表面附近的主体中的扩散区域及其制造方法。
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公开(公告)号：US20130307087A1
公开(公告)日：2013-11-21
申请号：US13471846
申请日：2012-05-15
申请人： Ruilong Xie , Su Chen Fan , Pranatharthiharan Haran Balasubramanian , David Vaclav Horak , Ponoth Shom
发明人： Ruilong Xie , Su Chen Fan , Pranatharthiharan Haran Balasubramanian , David Vaclav Horak , Ponoth Shom
IPC分类号： H01L27/088 , H01L21/311
CPC分类号： H01L21/823475 , H01L21/76897
摘要： A self-aligned source/drain contact formation process without spacer or cap loss is described. Embodiments include providing two gate stacks, each having spacers on opposite sides, and an interlayer dielectric (ILD) over the two gate stacks and in a space therebetween, forming a vertical contact opening within the ILD between the two gate stacks, and laterally removing ILD between the two gate stacks from the vertical contact opening toward the spacers, to form a contact hole.
摘要翻译： 描述了没有间隔物或盖损失的自对准源极/漏极接触形成过程。 实施例包括提供两个栅极堆叠，每个栅极堆叠在相对的两侧具有间隔物，以及位于两个栅极堆叠之间并在它们之间的空间中的层间电介质（ILD），在两个栅极堆叠之间的ILD内形成垂直接触开口，并横向移除ILD 在两个栅极堆叠之间从垂直接触开口朝向间隔件，形成接触孔。
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公开(公告)号：US20100176512A1
公开(公告)日：2010-07-15
申请号：US12351436
申请日：2009-01-09
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.
摘要翻译： 改进的半导体结构由上互连级别中的互连构成，所述互连通过使用位于上互连级别的通孔开口的底部的导电突起连接到下互连级别中的互连，所述导电突起从通孔的底部向上延伸 打开并进入通道开口。 与上下互连之间的导电突起的改进的互连结构增强了整体互连的可靠性。
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公开(公告)号：US08679968B2
公开(公告)日：2014-03-25
申请号：US13471846
申请日：2012-05-15
申请人： Ruilong Xie , Su Chen Fan , Pranatharthiharan Haran Balasubramanian , David Vaclav Horak , Ponoth Shom
发明人： Ruilong Xie , Su Chen Fan , Pranatharthiharan Haran Balasubramanian , David Vaclav Horak , Ponoth Shom
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/823475 , H01L21/76897
摘要： A self-aligned source/drain contact formation process without spacer or cap loss is described. Embodiments include providing two gate stacks, each having spacers on opposite sides, and an interlayer dielectric (ILD) over the two gate stacks and in a space therebetween, forming a vertical contact opening within the ILD between the two gate stacks, and laterally removing ILD between the two gate stacks from the vertical contact opening toward the spacers, to form a contact hole.
摘要翻译： 描述了没有间隔物或盖损失的自对准源极/漏极接触形成过程。 实施例包括提供两个栅极堆叠，每个栅极堆叠在相对的两侧具有间隔物，以及位于两个栅极堆叠之间并在它们之间的空间中的层间电介质（ILD），在两个栅极堆叠之间的ILD内形成垂直接触开口，并横向移除ILD 在两个栅极堆叠之间从垂直接触开口朝向间隔件，形成接触孔。
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公开(公告)号：US08021974B2
公开(公告)日：2011-09-20
申请号：US12351436
申请日：2009-01-09
IPC分类号： H01L21/02
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.
摘要翻译： 改进的半导体结构由上互连级别中的互连构成，所述互连通过使用位于上互连级别的通孔开口的底部的导电突起连接到下互连级别中的互连，所述导电突起从通孔的底部向上延伸 打开并进入通道开口。 与上下互连之间的导电突起的改进的互连结构增强了整体互连的可靠性。
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