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公开(公告)号：US08021974B2
公开(公告)日：2011-09-20
申请号：US12351436
申请日：2009-01-09
IPC分类号： H01L21/02
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.
摘要翻译： 改进的半导体结构由上互连级别中的互连构成，所述互连通过使用位于上互连级别的通孔开口的底部的导电突起连接到下互连级别中的互连，所述导电突起从通孔的底部向上延伸 打开并进入通道开口。 与上下互连之间的导电突起的改进的互连结构增强了整体互连的可靠性。
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公开(公告)号：US20100176512A1
公开(公告)日：2010-07-15
申请号：US12351436
申请日：2009-01-09
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.
摘要翻译： 改进的半导体结构由上互连级别中的互连构成，所述互连通过使用位于上互连级别的通孔开口的底部的导电突起连接到下互连级别中的互连，所述导电突起从通孔的底部向上延伸 打开并进入通道开口。 与上下互连之间的导电突起的改进的互连结构增强了整体互连的可靠性。
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公开(公告)号：US20130065376A1
公开(公告)日：2013-03-14
申请号：US13616882
申请日：2012-09-14
IPC分类号： H01L21/02
CPC分类号： H01L28/88 , H01L21/3105 , H01L21/31111 , H01L21/3212
摘要： A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor.
摘要翻译： 公开了一种半导体电容器及其制造方法。 使用非线性氮化物层来增加电容器板的表面积，导致增加的电容，而不增加用于电容器的芯片面积。
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公开(公告)号：US08518773B2
公开(公告)日：2013-08-27
申请号：US13616882
申请日：2012-09-14
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/88 , H01L21/3105 , H01L21/31111 , H01L21/3212
摘要： A method of fabricating a semiconductor capacitor includes forming a cavity in a first dielectric layer. Then, a nitride stack comprising a slow-etch nitride layer disposed between two fast-etch nitride layers is deposited in the cavity. Next, a portion of the nitride stack is etched within the cavity. Continuing, a metal plug is deposited in the cavity. The fast-etch nitride layers of the nitride stack are removed while preserving the slow-etch nitride layer of the nitride stack. A first metal layer is deposited over the slow-etch nitride layer, a second dielectric layer is deposited over the first metal layer, and a second metal layer is deposited over the second dielectric layer.
摘要翻译： 制造半导体电容器的方法包括在第一电介质层中形成空腔。 然后，将包括设置在两个快速蚀刻氮化物层之间的缓蚀刻氮化物层的氮化物堆叠沉积在空腔中。 接下来，在空腔内蚀刻氮化物叠层的一部分。 继续，金属塞被沉积在空腔中。 去除氮化物叠层的快速蚀刻氮化物层，同时保留氮化物叠层的缓蚀刻氮化物层。 在慢蚀刻氮化物层上沉积第一金属层，在第一金属层上沉积第二介电层，并且在第二介电层上沉积第二金属层。
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公开(公告)号：US08354703B2
公开(公告)日：2013-01-15
申请号：US13165191
申请日：2011-06-21
IPC分类号： H01L29/92
CPC分类号： H01L28/88 , H01L21/3105 , H01L21/31111 , H01L21/3212
摘要： A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor.
摘要翻译： 公开了一种半导体电容器及其制造方法。 使用非线性氮化物层来增加电容器板的表面积，导致增加的电容，而不增加用于电容器的芯片面积。
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公开(公告)号：US20120012979A1
公开(公告)日：2012-01-19
申请号：US12837121
申请日：2010-07-15
CPC分类号： H01L28/65 , H01L21/3105 , H01L21/31111 , H01L21/3212 , H01L28/88
摘要： An improved semiconductor capacitor and method of fabrication is disclosed. A nitride stack, comprising alternating sublayers of slow-etch and fast-etch nitride is deposited on a substrate. The nitride stack is etched via an anisotropic etch technique such as reactive ion etch. A wet etch then etches the nitride stack, forming a corrugated shape. The corrugated shape increases surface area, and hence increases the capacitance of the capacitor.
摘要翻译： 公开了一种改进的半导体电容器和制造方法。 包括交替的缓慢蚀刻和快速蚀刻氮化物的子层的氮化物堆叠沉积在衬底上。 通过诸如反应离子蚀刻的各向异性蚀刻技术蚀刻氮化物层。 湿蚀刻然后蚀刻氮化物叠层，形成波纹形状。 波纹形状增加了表面积，因此增加了电容器的电容。
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公开(公告)号：US20120012980A1
公开(公告)日：2012-01-19
申请号：US13165191
申请日：2011-06-21
CPC分类号： H01L28/88 , H01L21/3105 , H01L21/31111 , H01L21/3212
摘要： A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor.
摘要翻译： 公开了一种半导体电容器及其制造方法。 使用非线性氮化物层来增加电容器板的表面积，导致增加的电容，而不增加用于电容器的芯片面积。
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公开(公告)号：US08482132B2
公开(公告)日：2013-07-09
申请号：US12575980
申请日：2009-10-08
申请人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
发明人： Chih-Chao Yang , David V. Horak , Takeshi Nogami , Shom Ponoth
CPC分类号： H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/05007 , H01L2224/05014 , H01L2224/0502 , H01L2224/05099 , H01L2224/05547 , H01L2224/05554 , H01L2224/0556 , H01L2224/05599 , H01L2224/08121 , H01L2224/80001 , H01L2224/80345 , H01L2224/80357 , H01L2224/80359 , H01L2224/80895 , H01L2224/80896 , H01L2224/821 , H01L2224/9212 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/1305 , H01L2924/1306 , H01L2924/00 , H01L2224/80 , H01L2224/82
摘要： Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad.
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公开(公告)号：US20120175775A1
公开(公告)日：2012-07-12
申请号：US13424651
申请日：2012-03-20
申请人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/532
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.
摘要翻译： 包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料 线路各部分的电迁移效应。
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公开(公告)号：US20110193230A1
公开(公告)日：2011-08-11
申请号：US12700792
申请日：2010-02-05
申请人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
发明人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L24/80 , H01L21/0337 , H01L21/31144 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L23/53295
摘要： A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant.
摘要翻译： 提供了一种用于制造其电介质层中具有气隙的微电子元件的方法。 可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层的表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并且延伸第二高度 电介质层的表面的高度，第二高度大于第一高度。 在形成盖层之后，可以在盖层之上形成掩模。 掩模可以具有多个随机布置的孔。 每个孔可以暴露仅具有较大高度的盖层的第二部分的表面。 掩模可以完全覆盖具有较低高度的盖层的第一部分的表面。 随后，可以将蚀刻剂引导到盖层的第一和第二部分，以在盖层中形成与掩模中的孔对准的孔。 可以通过盖层中的孔从暴露于蚀刻剂的介电层去除材料。 此时，掩模可以保护盖层的第一部分和金属线不被蚀刻剂侵蚀。
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