公开(公告)号：US20090112583A1

公开(公告)日：2009-04-30

申请号：US12224785

申请日：2007-02-22

申请人： Yousuke Sakao ,  Kenji Satoh ,  Takahiro Ikeda ,  Yoshihiro Ikeda ,  Satoshi Nakazawa

发明人： Yousuke Sakao ,  Kenji Satoh ,  Takahiro Ikeda ,  Yoshihiro Ikeda ,  Satoshi Nakazawa

IPC分类号： G10L15/00 ,  G06F17/00

CPC分类号： G06F17/27 ,  G06F16/30

摘要： A language processing system, method, and program to automatically in time obtain text analysis results. The system comprises a plurality of text analysis units, each performing a different type of text analysis processing, an analysis order control means controlling order of analysis of text by each of the text analysis means, and an additional processing execution means receiving and executing additional processing for the text analysis results from each of the text analysis means, from a user. At a stage which a text analysis result by any one of said text analysis units is outputted and said additional processing execution unit operates, said analysis order control unit performs control to start text analysis processing for other text analysis means.

摘要翻译： 一种语言处理系统，方法和程序，能够及时获取文本分析结果。 该系统包括多个文本分析单元，每个文本分析单元执行不同类型的文本分析处理，分析顺序控制装置控制每个文本分析装置分析文本的顺序，以及附加处理执行装置，其接收和执行附加处理 对于来自每个文本分析手段的文本分析结果，来自用户。 在由所述文本分析单元中的任何一个输出文本分析结果并且所述附加处理执行单元进行操作的阶段，所述分析顺序控制单元进行控制以开始其他文本分析单元的文本分析处理。

公开(公告)号：US20090110962A1

公开(公告)日：2009-04-30

申请号：US11930449

申请日：2007-10-31

申请人： Hong Deng ,  Yoshihiro Ikeda

发明人： Hong Deng ,  Yoshihiro Ikeda

IPC分类号： G11B5/62 ,  B05D1/36 ,  G11B5/82 ,  B32B7/00

CPC分类号： G11B5/667 ,  G11B5/7325 ,  Y10T428/24

摘要： A perpendicular media is formed without an adhesion layer between the substrate and soft underlayer (SUL) to reduce the cost of fabrication. The thickness of the SUL is reduced to less than 50 nm to increase the film adhesion strength between the substrate and SUL. The perpendicular media comprises only a substrate, the SUL, an exchange break layer, a recording layer, and a protective overcoat.

摘要翻译： 在基板和软底层（SUL）之间形成没有粘附层的垂直介质，以降低制造成本。 SUL的厚度减小到小于50nm，以增加基板和SUL之间的膜粘附强度。 垂直介质仅包括基底，SUL，交换断裂层，记录层和保护性外涂层。

公开(公告)号：US07411242B2

公开(公告)日：2008-08-12

申请号：US11239338

申请日：2005-09-30

申请人： Takashi Kobayashi ,  Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Yoshihiro Ikeda ,  Kenji Kanamitsu

发明人： Takashi Kobayashi ,  Yoshitaka Sasago ,  Tsuyoshi Arigane ,  Yoshihiro Ikeda ,  Kenji Kanamitsu

IPC分类号： H01L29/76

CPC分类号： H01L27/11526 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/42324

摘要： The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.

摘要翻译： 本发明的目的是提供一种新的非易失性半导体存储器件及其制造方法，其目的是使三层多晶硅栅极的虚拟接地型存储单元小型化，提高性能，提高产量。 在根据本发明的存储器单元中，垂直于字线和沟道的浮动栅极的两个端面部分地通过电介质膜放置在第三栅极的顶部上。 本发明可以减少非易失性半导体存储器件的存储单元面积，提高工作速度，提高产量。

公开(公告)号：US20070027263A1

公开(公告)日：2007-02-01

申请号：US10571068

申请日：2004-09-01

申请人： Ryuji Furukawa ,  Masakuni Ueno ,  Katsumi Yamaguchi ,  Chiho Yoshimi ,  Yoshihiro Ikeda

发明人： Ryuji Furukawa ,  Masakuni Ueno ,  Katsumi Yamaguchi ,  Chiho Yoshimi ,  Yoshihiro Ikeda

IPC分类号： C08F297/00

CPC分类号： C08C1/14 ,  C08C1/15 ,  C08J3/14 ,  C08J3/16 ,  C08J9/16 ,  C08J2321/02 ,  C08J2351/00

摘要： A process for efficiently producing an agglomerate resulting from removal of impurities from a water-base latex of rubbery polymer particles or dry powder thereof and producing a dispersion having rubbery polymer particles dispersed in an organic solvent, and a process for efficiently producing a resin composition of low impurity content, in which the state of dispersion of rubbery polymer particles is excellent, from the above dispersion. In particular, a rubbery polymer particle agglomerate of low impurity content is obtained by first mixing a water-base latex of rubbery polymer particles with an organic solvent exhibiting partial solubility in water, bringing the resultant mixture into contact with water to thereby form a rubbery polymer particle agglomerate, and thereafter separating the water phase from the agglomerate/water phase mixture. Further, a resin composition of low impurity content having rubbery polymer particles favorably dispersed is obtained by first adding an organic solvent to the above agglomerate, mixing the obtained dispersion with a polymerizable organic compound having a reactive group, such as an epoxy resin, and thereafter distilling off volatile components.

摘要翻译： 一种有效地制造由橡胶状聚合物颗粒或其干粉末的水性胶乳除去杂质而产生的附聚物的方法，并且制备分散在有机溶剂中的具有橡胶状聚合物颗粒的分散体的方法，以及有效地制备 由于上述分散体，橡胶状聚合物粒子的分散状态优异的杂质含量低。 特别地，通过首先将橡胶状聚合物颗粒的水性胶乳与在水中显示部分溶解性的有机溶剂混合，使得到的混合物与水接触，从而形成橡胶状聚合物，得到低杂质含量的橡胶状聚合物颗粒聚集体 颗粒附聚物，然后从附聚物/水相混合物中分离出水相。 此外，通过首先向上述附聚物中加入有机溶剂，将得到的分散体与具有反应性基团的可聚合有机化合物如环氧树脂混合，然后将其混合，得到具有良好分散的橡胶状聚合物颗粒的低杂质含量的树脂组合物 蒸馏掉挥发性成分。

公开(公告)号：US20060104118A1

公开(公告)日：2006-05-18

申请号：US11257020

申请日：2005-10-25

申请人： Yoshihiro Ikeda ,  Hiroshi Ishida

发明人： Yoshihiro Ikeda ,  Hiroshi Ishida

IPC分类号： G11C16/06

CPC分类号： H01L27/11526 ,  G11C16/10 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11529

摘要： A non-volatile semiconductor memory device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, a plurality of memory cells formed on the semiconductor substrate, a plurality of first assist gates extending toward the memory cell, a connection portion connecting end portions of the first assist gates, a second assist gate extending toward the memory cell, a first select transistor controlling whether to apply a voltage to an area under the first assist gate, a second select transistor controlling whether to apply a voltage to an area under the second assist gate, and an impurity region. The insulating film formed under an intersection area of the connection portion and the impurity region has a thickness larger than the insulating film formed under the first and second assist gates. A non-volatile semiconductor memory device capable of ensuring a writing speed as well as reliability can thus be obtained.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的绝缘膜，形成在半导体衬底上的多个存储单元，朝向存储单元延伸的多个第一辅助栅极，连接端部 第一辅助栅极的第二辅助栅极，朝向存储单元延伸的第二辅助栅极，控制是否向第一辅助栅极下方的区域施加电压的第一选择晶体管，控制是否向下方的区域施加电压的第二选择晶体管 第二辅助栅极和杂质区域。 形成在连接部分和杂质区域的交叉区域下方的绝缘膜的厚度大于形成在第一和第二辅助栅极下方的绝缘膜的厚度。 因此可以获得能够确保写入速度以及可靠性的非易失性半导体存储器件。

公开(公告)号：US07015090B2

公开(公告)日：2006-03-21

申请号：US10408353

申请日：2003-04-08

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Yoshihiro Ikeda ,  Keisuke Tsukamoto ,  Tatsuya Fukumura ,  Shoji Shukuri ,  Keiichi Haraguchi ,  Koji Kishi

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Yoshihiro Ikeda ,  Keisuke Tsukamoto ,  Tatsuya Fukumura ,  Shoji Shukuri ,  Keiichi Haraguchi ,  Koji Kishi

IPC分类号： H01L21/8248

CPC分类号： H01L27/11536 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L29/66181 ,  H01L29/7833

摘要： At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage gate insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric film of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.

摘要翻译： 在电容器形成区域的表面上形成至少不少于一个形成凹凸表面的电容器形成沟槽。 因此，电容器的表面积增加，这能够提高每单位面积的电容器的电容。 此外，通过形成通过相同的步骤形成在半导体衬底的表面中的电容器形成沟槽和元件形成沟槽，可以简化制造工艺。 而电容器形成区域中的电容器的电介质膜和MISFET形成区域中的高压栅极绝缘膜通过相同的步骤形成; 或者，电容器形成区域中的电容器的电介质膜和存储单元形成区域中的多晶硅层和多晶硅层之间的存储器栅极层间膜通过相同的步骤形成。

公开(公告)号：US20060048358A1

公开(公告)日：2006-03-09

申请号：US11188981

申请日：2005-07-25

申请人： Tetsuya Morimura ,  Yoshihiro Ikeda ,  Makoto Irie ,  Motonori Matsushita

发明人： Tetsuya Morimura ,  Yoshihiro Ikeda ,  Makoto Irie ,  Motonori Matsushita

IPC分类号： H04R17/00

CPC分类号： H03H9/177 ,  H03H3/04 ,  H03H9/131 ,  H03H9/132 ,  H03H9/56 ,  H03H2003/0428 ,  H04R17/10 ,  Y10T29/42 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49156

摘要： A method of manufacturing a piezoelectric resonator includes forming first electrodes larger than vibrating electrodes in an area D1 including the vibrating electrodes on obverse and reverse surfaces of a piezoelectric substrate, and measuring the resonant frequency fr1 of a resonator including the first electrodes. The thickness of a metallic thin film required for frequency adjustment is determined based on the measured resonant frequency. Then, second electrodes formed of the metallic thin film having the determined thickness are formed in an area D2 including at least the vibrating electrodes of the piezoelectric substrate. By removing unnecessary portions of the first and second electrodes, a pattern of the resulting vibrating electrodes is formed. Thus, high-accuracy frequency adjustment can be achieved without the need for complicated positioning.

摘要翻译： 一种制造压电谐振器的方法包括在压电基板的正面和反面上形成包括振动电极的区域D 1中的比振动电极大的第一电极，并测量压电基片的谐振频率fr1 包括第一电极的谐振器。 基于所测得的谐振频率来确定频率调节所需的金属薄膜的厚度。 然后，由具有确定厚度的金属薄膜形成的第二电极形成在至少包括压电基板的振动电极的区域D 2中。 通过去除第一和第二电极的不需要的部分，形成所得到的振动电极的图案。 因此，可以实现高精度的频率调整，而不需要复杂的定位。

公开(公告)号：US6127255A

公开(公告)日：2000-10-03

申请号：US943729

申请日：1997-10-03

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/4763 ,  H01L21/469

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由元件分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的有源区的主表面上形成MISFET。 所公开的方法包括在包括最上面布线的布线上形成绝缘膜，最上面的布线在相邻最上布线之间具有间隙。 绝缘膜包括在布线和相邻的最上布线之间的间隙中形成氧化硅膜，并且在氧化硅膜上形成氮化硅膜，通过等离子体化学气相沉积形成氮化硅膜。 氧化硅膜形成为具有至少相邻最上面布线之间的间隙的一半的厚度，其中氮化硅膜比氧化硅膜厚。

公开(公告)号：US5739589A

公开(公告)日：1998-04-14

申请号：US657194

申请日：1996-06-03

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US5202275A

公开(公告)日：1993-04-13

申请号：US496330

申请日：1990-03-20

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/336 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/29 ,  H01L23/495 ,  H01L23/525 ,  H01L23/532 ,  H01L23/544 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L27/0922 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0928 ,  H01L27/10808 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在所述衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区和非活性区域的全部表面部分中的方式，在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。