公开(公告)号：US07323737B2

公开(公告)日：2008-01-29

申请号：US11517209

申请日：2006-09-06

申请人： Cem Basceri ,  F. Daniel Gealy ,  Gurtej S. Sandhu

发明人： Cem Basceri ,  F. Daniel Gealy ,  Gurtej S. Sandhu

IPC分类号： H01L27/108 ,  H01L23/48 ,  H01L21/8234

CPC分类号： H01L27/10855 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/57

摘要： The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.

摘要翻译： 本发明包括其中金属氧化物电介质材料沉积在阻挡层上的方法。 阻挡层可以包括金属和碳，硼和氮中的一种或多种的组合物，并且介电材料的金属氧化物可以包含与阻挡层相同的金属。 电介质材料/阻挡层结构可以结合到电容器中。 电容器可以用在例如DRAM单元中，DRAM单元又可以用在电子系统中。

公开(公告)号：US20070281220A1

公开(公告)日：2007-12-06

申请号：US11445907

申请日：2006-06-02

申请人： Gurtej S. Sandhu ,  Steve Kramer

发明人： Gurtej S. Sandhu ,  Steve Kramer

IPC分类号： G03F7/26

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088

摘要： A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To form the seed layer, diblock copolymers, composed of two immiscible blocks, are deposited in the space between copolymer alignment guides. The copolymers are made to self-organize, with the guides guiding the self-organization and with each block aggregating with other blocks of the same type, thereby forming the seed layer. Next, additional, supplemental diblock copolymers are deposited over the seed layer. The copolymers in the seed layer guide self-organization of the supplemental copolymers, thereby vertically extending the pattern formed by the copolymers in the seed layer. Block species are subsequently selectively removed to form a pattern of voids defined by the remaining block species, which form a mask that can be used to pattern an underlying substrate. The supplemental copolymers augment the height of the copolymers in the seed layer, thereby facilitating the use of the copolymers for patterning the underlying substrate.

摘要翻译： 在部分制造的集成电路上形成具有由诸如二嵌段共聚物之类的自组织材料形成的特征的掩模。 最初，在部分制造的集成电路的表面上形成共聚物模板或种子层。 为了形成种子层，由共混物对准引导件之间的空间中沉积由两个不混溶的嵌段组成的二嵌段共聚物。 使共聚物自组织，引导引导自组织，每个块与相同类型的其它嵌段聚集，从而形成种子层。 接下来，在种子层上沉积另外的补充二嵌段共聚物。 种子层中的共聚物引导辅助共聚物的自组织，从而在种子层中垂直延伸由共聚物形成的图案。 随后选择性地去除块物质以形成由剩余的嵌段物质限定的空隙图案，其形成可用于对下面的基底进行图案化的掩模。 补充共聚物增加了种子层中共聚物的高度，从而有利于共聚物用于图案化下面的底物。

公开(公告)号：US07303991B2

公开(公告)日：2007-12-04

申请号：US10863048

申请日：2004-06-07

申请人： Demetrius Sarigiannis ,  Garo J. Derderian ,  Cem Basceri ,  Gurtej S. Sandhu ,  F. Daniel Gealy ,  Chris M. Carlson

发明人： Demetrius Sarigiannis ,  Garo J. Derderian ,  Cem Basceri ,  Gurtej S. Sandhu ,  F. Daniel Gealy ,  Chris M. Carlson

IPC分类号： H01L21/44

CPC分类号： H01L21/32051 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45531 ,  C23C16/45534 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/31616

摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.

摘要翻译： 本发明包括在基板上形成沉积的组合物层的原子层沉积方法。 该方法包括将半导体衬底定位在原子层沉积室内。 在基材上形成中间体组合物单层，随后是与中间体组合物反应所需的沉积组合物，共同地将多个不同的组合物沉积前体流入沉积室内的基底。 材料粘附到室内部件表面，从而依次形成。 在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中并且有效地与这种粘附材料反应的室。 在反应气体流动之后，重复这种顺序形成。 考虑进一步的实现。

公开(公告)号：US07271077B2

公开(公告)日：2007-09-18

申请号：US10734999

申请日：2003-12-12

申请人： Eugene Marsh ,  Brian Vaartstra ,  Paul J. Castrovillo ,  Cem Basceri ,  Garo J. Derderian ,  Gurtej S. Sandhu

发明人： Eugene Marsh ,  Brian Vaartstra ,  Paul J. Castrovillo ,  Cem Basceri ,  Garo J. Derderian ,  Gurtej S. Sandhu

IPC分类号： H01L21/36 ,  H01L21/20

CPC分类号： C30B25/14 ,  C23C16/45527 ,  C30B25/02

摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. The first precursor gas flowing comprises a plurality of first precursor gas pulses. The plurality of first precursor gas pulses comprises at least one total period of time between two immediately adjacent first precursor gas pulses when no gas is fed to the chamber. After forming the first monolayer on the substrate, a second precursor gas different in composition from the first is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.

摘要翻译： 原子层沉积方法包括将半导体衬底定位在原子层沉积室内。 第一前体气体流到原子层沉积室内的衬底，有效地在衬底上形成第一单层。 第一前体气体流动包括多个第一前体气体脉冲。 多个第一前体气体脉冲包括当没有气体被供给到腔室时在两个紧邻的第一前体气体脉冲之间的至少一个总时间段。 在衬底上形成第一单层之后，组成不同于第一衬底的第二前体气体流入沉积室内的衬底，有效地在第一单层上形成第二单层。 考虑了其他方面和实现。

公开(公告)号：US07268388B2

公开(公告)日：2007-09-11

申请号：US10926675

申请日：2004-08-26

申请人： Cem Basceri ,  Gurtej S. Sandhu

发明人： Cem Basceri ,  Gurtej S. Sandhu

IPC分类号： H01L29/792

CPC分类号： G11C11/5671 ,  G11C8/12 ,  G11C16/0416 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/792

摘要： One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.

摘要翻译： 单晶体管存储器件通过操纵场效应晶体管（FET）的俘获层内的氧空位来促进非易失性数据存储，从而提供晶体管的阈值电压的控制和变化。 可以为各种阈值电压分配数据值，提供将一个或多个位数据存储在单个存储器单元中的能力。 为了控制阈值电压，可以通过在空位内捕获电子来操纵氧空位，从空位释放被俘获的电子，移动捕获层内的空位并湮灭空位。

公开(公告)号：US07253085B2

公开(公告)日：2007-08-07

申请号：US11326739

申请日：2006-01-05

申请人： Eric R. Blomiley ,  Gurtej S. Sandhu ,  Cem Basceri ,  Nirmal Ramaswamy

发明人： Eric R. Blomiley ,  Gurtej S. Sandhu ,  Cem Basceri ,  Nirmal Ramaswamy

IPC分类号： H01L21/36 ,  C30B21/20

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.

摘要翻译： 本发明包括半导体材料的选择性沉积方法。 将基板放置在反应室内。 基板包括第一表面和第二表面。 第一表面和第二表面在半导体材料前体暴露于其中来自前体的半导体材料的生长在生长阶段之前包含滞后期的条件下，并且在该阶段生长阶段在第二表面上开始需要更长时间比 在第一个表面。 进行第一表面和第二表面的曝光足够长的时间，以使生长阶段在第一表面上发生，但是不足以使生长相发生在第二表面上。

公开(公告)号：US07220670B2

公开(公告)日：2007-05-22

申请号：US10930443

申请日：2004-08-31

申请人： Gurtej S. Sandhu ,  Trung T. Doan

发明人： Gurtej S. Sandhu ,  Trung T. Doan

IPC分类号： H01L21/44

CPC分类号： H01L28/82 ,  C23C16/24 ,  C23C16/515 ,  H01L21/28525 ,  Y10S438/964

摘要： A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.

摘要翻译： 公开了一种在基板上沉积粗多晶硅膜的方法。 该方法包括将反应气体氩和硅烷引入沉积室，并且在沉积过程中在不同时间启用和禁用等离子体。

公开(公告)号：US07217615B1

公开(公告)日：2007-05-15

申请号：US09653149

申请日：2000-08-31

申请人： Garo J. Derderian ,  Gurtej S. Sandhu

发明人： Garo J. Derderian ,  Gurtej S. Sandhu

IPC分类号： H01L21/8242

CPC分类号： H01L28/56 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/28568 ,  H01L21/31604 ,  H01L28/75 ,  H01L28/84

摘要： A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. The barrier layer may be sufficiently thick and dense to reduce oxidation of the first electrode by oxygen diffusion from over the barrier layer. An alternative method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer and a second capacitor electrode may be formed over the dielectric layer. The method may further include forming rugged polysilicon over the substrate, the first electrode being over the rugged polysilicon. Accordingly, the outer surface area of the first electrode can be at least 30% greater than the outer surface area of the substrate without the first electrode including polysilicon.

摘要翻译： 电容器制造方法可以包括在第一电极上的氧扩散的原子层沉积导电阻挡层。 一种方法可以包括在第一电极上化学吸附至少一层单层的第一前体层，并化学吸附第一前体层上至少一层单层的第二前体层，第一和第二前体层的化学吸附产物 由导电阻挡材料层组成。 阻挡层可以是足够厚且致密的，以通过从阻挡层上方的氧扩散来减少第一电极的氧化。 替代方法可以包括在衬底上形成第一电容器电极，第一电极具有每单位面积的内表面积和每单位面积的外表面积，其大于衬底每单位面积的外表面积。 可以在电介质层上形成电容器电介质层和第二电容器电极。 该方法还可以包括在衬底上形成坚固的多晶硅，第一电极在坚固的多晶硅之上。 因此，第一电极的外表面积可以比不含第一电极包括多晶硅的衬底的外表面积大至少30％。

公开(公告)号：US07151054B2

公开(公告)日：2006-12-19

申请号：US10805557

申请日：2004-03-19

申请人： Gurtej S. Sandhu ,  Sujit Sharan

发明人： Gurtej S. Sandhu ,  Sujit Sharan

IPC分类号： H01L21/4763

CPC分类号： G03F7/091 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/28123 ,  H01L21/3145

摘要： In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma during deposition of a silicon, nitrogen and oxygen containing solid layer over a substrate.In another aspect, the invention includes a gate stack forming method, comprising: a) forming a polysilicon layer over a substrate; b) forming a metal silicide layer over the polysilicon layer; c) depositing an antireflective material layer over the metal silicide utilizing a high density plasma; d) forming a layer of photoresist over the antireflective material layer; e) photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist; and f) transferring a pattern from the patterned masking layer to the antireflective material layer, metal silicide layer and is polysilicon layer to pattern the antireflective material layer, metal silicide layer and polysilicon layer into a gate stack.

摘要翻译： 在一个方面，本发明包括一种半导体处理方法，包括在衬底上沉积含硅，含氮和氧的固体层时，将硅，氮和氧气体暴露于高密度等离子体。 在另一方面，本发明包括一种栅堆叠形成方法，包括：a）在衬底上形成多晶硅层; b）在所述多晶硅层上形成金属硅化物层; c）利用高密度等离子体在金属硅化物上沉积防反射材料层; d）在抗反射材料层上形成一层光致抗蚀剂; e）光刻地图案化所述光致抗蚀剂层以从所述光致抗蚀剂层形成图案化掩模层; 以及f）将图案从图案化掩模层转移到抗反射材料层，金属硅化物层，并且是将抗反射材料层，金属硅化物层和多晶硅层图案化成栅叠层的多晶硅层。

公开(公告)号：US07115529B2

公开(公告)日：2006-10-03

申请号：US10629011

申请日：2003-07-28

申请人： Trung Tri Doan ,  Guy T. Blalock ,  Gurtej S. Sandhu

发明人： Trung Tri Doan ,  Guy T. Blalock ,  Gurtej S. Sandhu

IPC分类号： H01L21/469

CPC分类号： H01L21/0228 ,  C23C16/38 ,  C23C16/403 ,  C23C16/45542 ,  C23C16/515 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/31683 ,  H01L21/76841

摘要： A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber effective to react with the first monolayer and form a second monolayer on the substrate which is different in composition from the first monolayer. The second monolayer includes components of the first monolayer and the second precursor. In one implementation, the first and second precursor flowings are successively repeated effective to form a mass of material on the substrate of the second monolayer composition. Additional and other implementations are contemplated.