Method for fabricating dual damascene structures
    97.
    发明授权
    Method for fabricating dual damascene structures 失效
    双镶嵌结构的制作方法

    公开(公告)号:US07727708B2

    公开(公告)日:2010-06-01

    申请号:US12121502

    申请日:2008-05-15

    IPC分类号: G03F7/26

    CPC分类号: G03F7/094 G03F1/50

    摘要: A method for fabricating a dual damascene structure includes providing a multi-layer photoresist stack comprising a first photoresist layer and a second photoresist layer, wherein each photoresist layer has a distinct dose-to-clear value, exposing said photoresist stack to one or more predetermined patterns of light, and developing said photo-resist layers to form a multi-tiered structure in the photo-resist layers.

    摘要翻译: 一种用于制造双镶嵌结构的方法包括提供包括第一光致抗蚀剂层和第二光致抗蚀剂层的多层光致抗蚀剂层,其中每个光致抗蚀剂层具有不同的剂量至清除值,将所述光致抗蚀剂层暴露于一个或多个预定的 并且显影所述光致抗蚀剂层以在光致抗蚀剂层中形成多层结构。

    Microelectronic circuit structure with layered low dielectric constant regions
    98.
    发明授权
    Microelectronic circuit structure with layered low dielectric constant regions 失效
    微电子电路结构具有层状低介电常数区域

    公开(公告)号:US07692308B2

    公开(公告)日:2010-04-06

    申请号:US12256735

    申请日:2008-10-23

    IPC分类号: H01L29/40

    摘要: The circuit structure includes at least two generally parallel conductor structures, and a plurality of substantially horizontal layers of layer dielectric material interspersed with substantially horizontally extending relatively low dielectric constant (low-k) volumes. The substantially horizontal layers and the substantially horizontally extending volumes are generally interposed between the at least two generally parallel conductor structures. Also included are a plurality of substantially vertically extending relatively low-k volumes sealed within the substantially horizontal layers and the substantially horizontally extending volumes between the at least two generally parallel conductor structures. The substantially vertically extending relatively low-k volumes and the substantially horizontally extending relatively low-k volumes reduce parasitic capacitance between the at least two generally parallel conductor structures as compared to an otherwise comparable microelectronic circuit not including the relatively low-k volumes.

    摘要翻译: 电路结构包括至少两个大致平行的导体结构,以及多个基本上水平的层介质材料层,散布着基本上水平延伸的相对较低的介电常数(低k)体积。 基本水平的层和基本上水平延伸的体积通常介于至少两个大致平行的导体结构之间。 还包括在基本水平的层内密封的多个基本上垂直延伸的相对低k的体积,以及在至少两个大致平行的导体结构之间的基本水平延伸的体积。 与不包括相对低k体积的其他可比较的微电子电路相比,基本垂直延伸的相对低k体积和基本水平延伸的相对低k体积减小了至少两个大致平行的导体结构之间的寄生电容。

    Metal capping process for BEOL interconnect with air gaps
    99.
    发明授权
    Metal capping process for BEOL interconnect with air gaps 失效
    带气隙的BEOL互连金属封盖工艺

    公开(公告)号:US07666753B2

    公开(公告)日:2010-02-23

    申请号:US11622188

    申请日:2007-01-11

    IPC分类号: H01L21/76

    摘要: The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact the metal lines. In addition, air gaps are between the metal lines, wherein the air gaps are between the metal caps. A second dielectric is also provided over the bottom portion of a first dielectric, wherein a top portion of the second dielectric is over the metal caps, and wherein top portions of the first dielectric and bottom portions of the second dielectric comprise sides of the air gap. The apparatus further includes dielectric caps over the metal lines, wherein the dielectric caps contact the metal caps.

    摘要翻译: 本发明的实施例提供了一种用于具有气隙的BEOL互连的金属封盖工艺。 更具体地,提供了一种包括在第一电介质内的金属线的装置。 金属盖在金属线上方,金属帽与金属线接触。 此外,气隙在金属线之间,其中气隙在金属盖之间。 第二电介质还设置在第一电介质的底部上方,其中第二电介质的顶部在金属帽之上,并且其中第二电介质的第一电介质和底部的顶部包括气隙的侧面 。 该装置还包括金属线上的电介质盖,其中介电帽与金属盖接触。