公开(公告)号：US10535771B1

公开(公告)日：2020-01-14

申请号：US16016828

申请日：2018-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02

Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

公开(公告)号：US10535674B2

公开(公告)日：2020-01-14

申请号：US15653661

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Frank Jakubowski

IPC: H01L27/11568 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/265 ,  H01L27/11521 ,  H01L27/12 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11582 ,  H01L49/02

Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

公开(公告)号：US10535379B2

公开(公告)日：2020-01-14

申请号：US15695457

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Darren L. Anand ,  John A. Fifield ,  Eric D. Hunt-Schroeder ,  Mark D. Jacunski

IPC: G11C7/06 ,  G11C17/18

Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

公开(公告)号：US20200013551A1

公开(公告)日：2020-01-09

申请号：US16550431

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil K. Singh ,  Jagar Singh

IPC: H01F41/063 ,  H01F41/12 ,  H01F5/00 ,  H01F5/06 ,  H01F41/34 ,  H01F17/00 ,  H01F41/04 ,  H01L49/02 ,  H01L21/00

Abstract: A first layer on a substrate includes an insulator material portion adjacent an energy-reactive material portion. The energy-reactive material portion evaporates upon application of energy during manufacturing. Processing patterns the first layer to include recesses extending to the substrate in at least the energy-reactive material portion. The recesses are filled with a conductor material, and a porous material layer is formed on the first layer and on the conductor material. Energy is applied to the porous material layer to: cause the energy to pass through the porous material layer and reach the energy-reactive material portion; cause the energy-reactive material portion to evaporate; and fully remove the energy-reactive material portion from an area between the substrate and the porous material layer, and this leaves a void between the substrate and the porous material layer and adjacent to the conductor material.

公开(公告)号：US10530373B1

公开(公告)日：2020-01-07

申请号：US16428975

申请日：2019-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ahmed Reda Fridi ,  Man Tran

IPC: H04B1/38 ,  H04B1/06 ,  H03L7/099 ,  H04B1/40 ,  H03K4/08 ,  H03L7/093

Abstract: A transceiver includes a frequency modulation continuous wave generator to generate a frequency sequence and a digital phase locked loop to generate a waveform based on the frequency sequence. The digital phase locked loop includes a plurality of control registers. A main controller captures a reference state defined in the plurality of configuration registers prior to the frequency sequence, initiates the frequency sequence, restores the reference state of the configuration registers after completion of the frequency sequence, and repeats the frequency sequence after restoring the reference state.

公开(公告)号：US10529831B1

公开(公告)日：2020-01-07

申请号：US16054881

申请日：2018-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qun Gao ,  Matthew W. Stoker ,  Haigou Huang

IPC: H01L29/78 ,  H01L29/66

Abstract: At least one method, apparatus and system providing semiconductor devices comprising a semiconductor substrate; a first fin and a second fin on the semiconductor substrate; a first epitaxial formation on the first fin and having an inner surface oriented toward the second fin and an outer surface oriented away from the second fin; a second epitaxial formation on the second fin and having an inner surface oriented toward the first fin and an outer surface oriented away from the first fin; and a conformal dielectric layer on at least portions of the inner and outer surfaces of the first epitaxial formation, on at least portions of the inner and outer surfaces of the first epitaxial formation and the second epitaxial formation, and merged between the inner surface of the first epitaxial formation and inner surface of the second epitaxial formation.

公开(公告)号：US20200004155A1

公开(公告)日：2020-01-02

申请号：US16022752

申请日：2018-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yong Liang ,  Lei Sun ,  Yongan Xu ,  Craig D. Higgins

IPC: G03F7/20 ,  G03F1/22

Abstract: Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is “self-biased”). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer. Movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer improves photoresist layer development and pattern resolution.

公开(公告)号：US10522538B1

公开(公告)日：2019-12-31

申请号：US16032108

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

公开(公告)号：US10522410B2

公开(公告)日：2019-12-31

申请号：US15958593

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Haiting Wang ,  Hong Yu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088

Abstract: A device is formed including fins formed above a substrate, an isolation structure between the fins, a plurality of structures defining gate cavities, and a first dielectric material positioned between the structures. A patterning layer above the first dielectric material and in the gate cavities has a first opening positioned above a first gate cavity exposing a portion of the isolation structure and defining a first recess, a second opening above a second gate cavity exposing a first portion of the fins, and a third opening above a first portion of a source/drain region in the fins to expose the first dielectric material. Using the patterning layer, a second recess is formed in the substrate and a third recess is defined in the first dielectric material. A second dielectric material is formed in the recesses to define a gate cut structure, a diffusion break structure, and a contact cut structure.

公开(公告)号：US20190393321A1

公开(公告)日：2019-12-26

申请号：US16014076

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Scott Beasor

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Various processes form different structures including exemplary apparatuses that include (among other components) a first layer having channel regions, source/drain structures in the first layer on opposite sides of the channel regions, a gate insulator on the channel region, and a gate stack on the gate insulator. The gate stack can include a gate conductor, and a stack insulator or a gate contact on the gate conductor. The gate stack has lower sidewalls adjacent to the source/drain structures and upper sidewalls distal to the source/drain structures. Further, lower spacers are between the source/drain contacts and the lower sidewalls of the gate stack; and upper spacers between the source/drain contacts and the upper sidewalls of the gate stack. In some structures, the upper spacers can partially overlap the lower spacers.