公开(公告)号：US20040153632A1

公开(公告)日：2004-08-05

申请号：US10757925

申请日：2004-01-16

申请人： MICROUNITY SYSTEMS ENGINEERING, INC.

发明人： Craig Hansen ,  John Moussouris

IPC分类号： G06F009/00

CPC分类号： G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

摘要： A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

摘要翻译： 一种用于通过结合执行单元来提高处理器的性能的系统和软件，所述执行单元可操作以解码和执行指定数据选择操作数的单个指令，以及提供多个数据元素的第一和第二寄存器，所述数据选择操作数包括多个字段 每个选择所述多个数据元素中的一个，所述执行单元可操作以将所述数据选择操作数的每个字段所选择的数据元素提供到预定位置。

公开(公告)号：US5867735A

公开(公告)日：1999-02-02

申请号：US20859

申请日：1998-02-09

申请人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

发明人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

IPC分类号： G06F9/38 ,  G06F15/00 ,  G06F15/20

CPC分类号： G06F9/3824

摘要： A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

摘要翻译： 提供非阻塞负载缓冲器用于高速微处理器和存储器系统。 非阻塞负载缓冲器将高速处理器/高速缓存总线接口，该总线将处理器和高速缓存连接到非阻塞负载缓冲区，其中低速外设总线连接到外围设备。 非阻塞负载缓冲器允许以相对较低带宽的外围设备从外围设备的最大速率直接从处理器的编程I / O检索数据，从而可以处理和存储数据，而不会使处理器无需空闲。 可以同时缓冲多处理器内的多个处理器的I / O请求，以便可以在设备的等待时间期间处理多个非阻塞负载。 因此，通过处理器的编程I / O实现来自多个I / O设备的连续最大吞吐量，并且可以减少完成任务和处理数据所需的时间。 此外，提供了多重优先级的非阻塞负载缓冲器，用于通过基于优先级的存储器和外设访问调度来服务运行不同期限的实时处理的多处理器。

公开(公告)号：US5821603A

公开(公告)日：1998-10-13

申请号：US655061

申请日：1996-05-29

申请人： Kumar D. Puntambekar

发明人： Kumar D. Puntambekar

IPC分类号： C23C16/34 ,  C23C16/44 ,  C23C16/455 ,  H01L21/033 ,  H01L21/318 ,  H01L21/768 ,  H01L23/58

CPC分类号： C23C16/45523 ,  C23C16/345 ,  H01L21/0337 ,  H01L21/3185 ,  H01L21/7688

摘要： Methods for depositing a nitride layer on a surface of an integrated circuit wafer for protecting against over etching during subsequent etching of overlying layers. A first nitride deposition method utilizes a chemical vapor deposition process having a variable ammonia flow rate. The ammonia flow rate is decreased during the chemical vapor deposition process. A second nitride deposition method produces an oxygen rich etch stop film on the surface of the nitride layer. The method comprises the application of an oxygen/argon plasma treatment to the surface of the nitride layer in a reactive ion etching process. A third nitride deposition method produces an oxygen rich etch stop film on the surface of the nitride layer. The method comprises the application of a nitrous oxide plasma treatment to the surface of the nitride layer in a chemical vapor deposition chamber.

摘要翻译： 用于在集成电路晶片的表面上沉积氮化物层的方法，用于在随后的上覆层的蚀刻期间防止过度蚀刻。 第一氮化物沉积方法利用具有可变氨流速的化学气相沉积工艺。 在化学气相沉积过程中氨流速降低。 第二氮化物沉积方法在氮化物层的表面上产生富氧蚀刻停止膜。 该方法包括在反应离子蚀刻工艺中对氮化物层的表面施加氧/氩等离子体处理。 第三氮化物沉积方法在氮化物层的表面上产生富氧蚀刻停止膜。 该方法包括在化学气相沉积室中对氮化物层的表面施加一氧化二氮等离子体处理。

公开(公告)号：US5812799A

公开(公告)日：1998-09-22

申请号：US480738

申请日：1995-06-07

申请人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

发明人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

IPC分类号： G06F13/42 ,  H01J13/00

CPC分类号： G06F13/4243

摘要： A non-blocking load buffer for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

摘要翻译： 用于高速微处理器和存储器系统的非阻塞负载缓冲器。 非阻塞负载缓冲器将高速处理器/高速缓存总线接口，该总线将处理器和高速缓存连接到非阻塞负载缓冲区，其中低速外设总线连接到外围设备。 非阻塞负载缓冲器允许以相对较低带宽的外围设备从外围设备的最大速率直接从处理器的编程I / O检索数据，从而可以处理和存储数据，而不会使处理器无需空闲。 可以同时缓冲多处理器内的多个处理器的I / O请求，以便可以在设备的等待时间期间处理多个非阻塞负载。 因此，通过处理器的编程I / O实现来自多个I / O设备的连续最大吞吐量，并且可以减少完成任务和处理数据所需的时间。 此外，提供了多重优先级的非阻塞负载缓冲器，用于通过基于优先级的存储器和外设访问调度来服务运行不同期限的实时处理的多处理器。

公开(公告)号：US5663893A

公开(公告)日：1997-09-02

申请号：US433730

申请日：1995-05-03

申请人： Kurt E. Wampler ,  Thomas L. Laidig

发明人： Kurt E. Wampler ,  Thomas L. Laidig

IPC分类号： G03F1/00 ,  G03F7/20 ,  H01L21/027 ,  G03F7/00 ,  H01J37/302

CPC分类号： G03F7/70441 ,  G03F1/36 ,  H01J2237/31762 ,  H01J2237/31769

摘要： A method for synthesizing correction features for an entire mask pattern that initially divides mask pattern data into tiles of data--each tile representing an overlapping section of the original mask pattern. Each of the tiles of data is sequentially processed through correction feature synthesis phases--each phase synthesizing a different type of correction feature. All of the correction features are synthesized for a given tile before synthesizing the correction features for the next tile. Each correction feature synthesis phase formats the data stored in the tile into a representation that provides information needed to synthesize the correction feature for the given phase. Methods for implementing edge bar and serif correction features synthesis phases are also described. The method for synthesizing external type edge bars is performed by oversizing feature data in the tile by an amount equal to the desired spacing of the external edge bar, formatting the oversized data into an edge representation and expanding each of the edges in the edge representation of the oversized data into edge bars having a predetermined width. Internal type of edge bars for the tile are synthesized by initially inverting feature data and then performing the same steps as for generating the external edge bars. The method for serif synthesis is performed by initially formatting tile data into a vertex representation, eliminating certain of the vertices not requiring serifs, synthesizing a positive serif for each convex corner and a negative vertex for each concave corner, and eliminating any disallowed serifs. Internal bars and negative serifs are "cut-out" of original tile data by performing geometric Boolean operations and external bars and positive serifs are concatenated with the "cut-out" tile data, equivalent to performing a geometric OR operation.

摘要翻译： 一种用于将最初将掩模图案数据划分成数据块的整个掩模图案的校正特征的方法，每个瓦片表示原始掩模图案的重叠部分。 通过校正特征合成阶段顺序地处理每个数据块，每个相合成不同类型的校正特征。 在合成下一个图块的修正特征之前，为给定的图块合成所有的修正特征。 每个校正特征合成阶段将存储在瓦片中的数据格式化为提供合成给定阶段的校正特征所需的信息的表示。 还描述了实现边缘条和衬线修正特征合成阶段的方法。 用于合成外部边缘条的方法是通过将平铺中的特征数据超过等于外部边缘条的期望间隔的量来执行的，将大尺寸数据格式化为边缘表示，并且将边缘表示中的每个边缘扩展 大尺寸数据成为具有预定宽度的边条。 通过初始反转特征数据然后执行与产生外边缘条相同的步骤来合成瓦片的边缘条的内部类型。 通过将瓦片数据初始格式化为顶点表示，消除某些不需要衬线的顶点，为每个凸角组合正衬线和每个凹角的负顶点，并消除任何不允许的衬线，执行衬线合成的方法。 内部条形和负衬里是通过执行几何布尔运算和外部条，原始瓦片数据“切出”，正衬线与“切出”瓦片数据相连，相当于执行几何或运算。

公开(公告)号：US5630096A

公开(公告)日：1997-05-13

申请号：US437975

申请日：1995-05-10

申请人： William K. Zuravleff ,  Timothy Robinson

发明人： William K. Zuravleff ,  Timothy Robinson

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/1626 ,  G06F13/28

摘要： A controller for a synchronous DRAM is provided for maximizing throughput of memory requests to the synchronous DRAM. The controller maintains the spacing between the commands to conform with the specifications for the synchronous DRAMs while preventing gaps from occurring in the data slots to the synchronous DRAM. Furthermore, the controller allows memory requests and commands to be issued out of order so that the throughput may be maximized by overlapping required operations which do not specifically involve data transfer. To achieve this maximized throughput, memory requests are tagged for indicating a sending order. Thereafter, the memory requests may be arbitrated when conflicting memory requests are queued and this arbitration process is then decoded for simultaneously updating scheduling constraints. The memory requests may be further qualified based on the scheduling constraints and a command stack of memory request is then developed for modifying update queues. The controller also functions by receiving a controller clock signal and generating an SDRAM clock signal by dividing this controller clock signal.

摘要翻译： 提供用于同步DRAM的控制器，用于最大化对同步DRAM的存储器请求的吞吐量。 控制器保持命令之间的间隔，以符合同步DRAM的规范，同时防止在数据时隙中发生间隙到同步DRAM。 此外，控制器允许存储器请求和命令被无序地发布，使得可以通过重叠不特别涉及数据传输的所需操作来最大化吞吐量。 为了实现这种最大化的吞吐量，存储器请求被标记以指示发送顺序。 此后，当冲突的存储器请求被排队时，可以对存储器请求进行仲裁，然后对该仲裁过程进行解码以便同时更新调度约束。 可以基于调度约束进一步限定存储器请求，然后开发用于修改更新队列的存储器请求的命令栈。 该控制器还通过接收控制器时钟信号并通过划分该控制器时钟信号来产生SDRAM时钟信号来起作​​用。

公开(公告)号：US5432736A

公开(公告)日：1995-07-11

申请号：US184436

申请日：1994-01-21

申请人： Ban P. Wong ,  John G. Campbell

发明人： Ban P. Wong ,  John G. Campbell

IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/41

摘要： A current mode access BiCMOS memory cell is disclosed. The memory cell includes a CMOS storage cell for storing first and second CMOS voltage potentials, VDD and VSS, corresponding to first and second logic levels. The storage cell includes two CMOS inverters coupled between VDD and VSS. The storage cell is coupled to a conversion circuit. The conversion circuit is coupled between third and fourth ECL working potentials. It functions to convert the first and second CMOS voltage potentials into the third and fourth working potentials. The third and fourth voltage potentials are coupled to the bases of two bipolar signal converters. The emitters of the bipolar signal converters are coupled to a selectable current source and the collectors of the bipolar signal converters are coupled to complementary bit lines. The selectable current source is responsive to a read word signal. A differential current signal representing the data stored in the memory cell is established in the complementary bit lines when the current source is selected and current is allowed to flow through one of the bipolar signal converters. The third and fourth ECL voltage potentials are chosen such that they ensure that the bipolar signal converters are not driven into saturation. In this way, read times are optimized. In addition, read times are reduced since peak-to-peak voltage of the current mode differential signal established across the complementary bit lines are reduced.

摘要翻译： 公开了一种电流模式存取BiCMOS存储单元。 存储单元包括用于存储对应于第一和第二逻辑电平的第一和第二CMOS电压电位VDD和VSS的CMOS存储单元。 存储单元包括耦合在VDD和VSS之间的两个CMOS反相器。 存储单元耦合到转换电路。 转换电路耦合在第三和第四ECL工作电位之间。 它用于将第一和第二CMOS电压电位转换为第三和第四工作电位。 第三和第四电压电位耦合到两个双极性信号转换器的基极。 双极性信号转换器的发射极耦合到可选择的电流源，并且双极性信号转换器的集电极耦合到互补位线。 可选择的电流源响应于读取字信号。 当选择电流源并且允许电流流过双极型信号转换器之一时，表示存储在存储单元中的数据的差分电流信号被建立在互补位线中。 选择第三和第四ECL电压电位，使得它们确保双极性信号转换器不被驱动到饱和。 以这种方式，优化了阅读时间。 此外，由于在互补位线上建立的电流模式差分信号的峰 - 峰电压降低，读取时间减少。

公开(公告)号：US5420587A

公开(公告)日：1995-05-30

申请号：US86139

申请日：1993-07-01

申请人： Jean Y. Michel

发明人： Jean Y. Michel

IPC分类号： H03M1/14 ,  H03M1/20 ,  H03M1/36

CPC分类号： H03M1/204 ,  H03M1/365

摘要： A two-stage flash analog-to-digital signal converter has a first stage voltage divider network and a set of amplifiers that perform an initial interpolation. The initial interpolation results are directly coupled, i.e. no resistive or capacitive elements, to a second stage comprising a set of comparators having multiple inputs. The multiple inputs of the second stage comparators are weightily coupled to the first stage amplifiers in a manner so as to cause the second stage comparators to generate a digital representation of the analog signal.

摘要翻译： 两级闪存模数转换器具有第一级分压网络和一组执行初始插值的放大器。 初始插值结果直接耦合到包括具有多个输入的一组比较器的第二级，即没有电阻或电容元件。 第二级比较器的多个输入以这样的方式重叠地耦合到第一级放大器，以便使第二级比较器产生模拟信号的数字表示。

公开(公告)号：US5410670A

公开(公告)日：1995-04-25

申请号：US071237

申请日：1993-06-02

申请人： Craig C. Hansen ,  John G. Campbell ,  Timothy B. Robinson

发明人： Craig C. Hansen ,  John G. Campbell ,  Timothy B. Robinson

IPC分类号： G11C11/413 ,  G11C5/02 ,  G11C7/00 ,  G11C7/10 ,  G11C29/00 ,  G06F12/06

CPC分类号： G11C7/1039 ,  G11C5/025

摘要： A large burst mode memory accessing system includes N discrete sub-memories and three main I/O ports. Data is stored in the sub-memories so that the sub-memories are accessed depending on their proximity to the main I/O ports. Three parallel pipelines provide a data path to/from the main I/O ports and the sub-memories. The first pipeline functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.

摘要翻译： 大型突发模式存储器存取系统包括N个离散子存储器和三个主要I / O端口。 数据存储在子存储器中，使得子存储器根据其与主I / O端口的接近度被访问。 三条并行的管道提供到/从主I / O端口和子存储器的数据路径。 第一流水线用于将地址/控制信号耦合到存储器，使得相邻子存储器以半周期间隔被访问。 第二流水线用于将访问数据从子存储器传播到主I / O端口，使得每个连续时钟周期从主输出端口输出数据。 第三流水线将写数据传播到存储器，使得在连续时钟周期的第三流水线的输入处呈现的数据被写入连续的子存储器。 冗余电路保留数据完整性，无需存储器访问中断。

公开(公告)号：US5182225A

公开(公告)日：1993-01-26

申请号：US647717

申请日：1991-01-28

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L29/417

CPC分类号： H01L21/28211 ,  H01L21/28525 ,  H01L21/768 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002

摘要： A method for forming a BICMOS integrated circuit having MOS field-effect devices and bipolar junction transistors formed in a silicon substrate is disclosed. The process comprises the steps of first defining separate active areas in a substrate for each of the transistors. Next, a gate dielectric layer is formed over the surface of the wafer. Above the gate dielectric, a first layer of polysilicon is deposited. This first layer of polysilicon is then selectively etched to form a plurality of first polysilicon members each of which is equally-spaced apart from one another. The polysilicon members comprise the gates of the MOS transistors and the extrinsic base contacts of the NPN transistors. After the first polysilicon members have been defined, the base regions of the NPN transistors are formed. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members which are electrically isolated from the first polysilicon members. Impurities are diffused from the polysilicon members into the substrate to form the source/drain regions of the MOS transistors, and the extrinsic base and emitter regions of the NPN transistors. The final processing steps include those required for the interconnection of the MOS and NPN transistors.

摘要翻译： 公开了一种用于形成具有MOS场效应器件和形成在硅衬底中的双极结型晶体管的BICMOS集成电路的方法。 该方法包括以下步骤：首先在每个晶体管的衬底中定义单独的有源区。 接下来，在晶片的表面上形成栅介质层。 在栅极电介质上方沉积第一层多晶硅。 然后选择性地蚀刻第一层多晶硅以形成多个第一多晶硅构件，每个第一多晶硅构件彼此相等间隔开。 多晶硅构件包括MOS晶体管的栅极和NPN晶体管的非本征基极触点。 在限定了第一多晶硅部件之后，形成NPN晶体管的基极区域。 在绝缘第一多晶硅部件之后，在衬底上沉积附加的多晶硅层以再次整个晶片表面。 然后蚀刻附加多晶硅层以形成与第一多晶硅构件电绝缘的多个第二多晶硅构件。 杂质从多晶硅部件扩散到衬底中以形成MOS晶体管的源极/漏极区域，以及NPN晶体管的非本征基极和发射极区域。 最后的处理步骤包括MOS和NPN晶体管互连所需的步骤。