公开(公告)号：US20180151601A1

公开(公告)日：2018-05-31

申请号：US15488629

申请日：2017-04-17

Applicant: AU Optronics Corporation

Inventor： Ming-Hsien LEE

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1333 ,  G02F1/1368

CPC classification number: H01L27/1248 ,  G02F1/133345 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/133357 ,  G02F2201/123 ,  H01L27/1218 ,  H01L27/124 ,  H01L29/78603 ,  H01L29/78621 ,  H01L29/78636

Abstract: A pixel structure is disposed on a substrate and includes a bump, a first insulating layer, a semiconductive layer, a second insulating layer, a metal layer, and a pixel electrode. The bump is disposed on the substrate. The first insulating layer is disposed on the substrate and covers the bump. The first insulating layer has a protruding portion at the position at which the first insulating layer covers the bump. The semiconductive layer is disposed on the first insulating layer, and at least a portion of the semiconductive layer is disposed above the protruding portion. The second insulating layer is disposed on the first insulating layer and covers the semiconductive layer. The second insulating layer has a via, so as to make a portion of the semiconductive layer be not covered by the second insulating layer. The via corresponds to the protruding portion in a direction perpendicular to the substrate. The metal layer is electrically connected to the semiconductive layer through the via.

公开(公告)号：US20180151591A1

公开(公告)日：2018-05-31

申请号：US15575421

申请日：2017-03-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Kun LIU

IPC: H01L27/12 ,  H01L23/31 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L27/124 ,  G02F1/136227 ,  G02F2001/134372 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L23/291 ,  H01L23/3171 ,  H01L27/1248 ,  H01L27/1262 ,  H01L27/1288

Abstract: An array substrate includes a substrate base, a gate layer, and a gate insulating layer, an active layer, a source-drain electrode layer, an etching barrier layer, a planarization layer, a first electrode layer, a passivation layer and a second electrode layer sequentially formed on the substrate, wherein, a via hole is formed in the etching barrier layer, the planarization layer and the passivation layer; and the first electrode layer comprises a common electrode pattern and an anti-etching pattern; the anti-etching pattern comprises a plurality of anti-etching structures, each of the anti-etching structures is correspondingly filled into one via hole; and the second electrode layer comprises a pixel electrode pattern, the pixel electrode in the pixel electrode pattern is electrically connected to the source-drain electrode layer through the anti-etching structure in the via hole.

公开(公告)号：US09983451B2

公开(公告)日：2018-05-29

申请号：US15194079

申请日：2016-06-27

Applicant: LG Display Co., Ltd.

Inventor： ChelHee Jo ,  KiTaeg Shin ,  Donggeun Lim ,  Jiwon Kang

IPC: G02F1/1362 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: G02F1/136259 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136295 ,  G02F2201/123 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: The present invention provides a method of reworking an array substrate including a gate metal layer, a gate insulation layer (G1), a semiconductor layer, a source/drain metal layer, a lower passivation layer, a common electrode layer, an upper passivation layer, and a pixel electrode layer sequentially formed therein. By using a rework mask protecting a jumping passivation hole area in reworking the pixel electrode layer, the method can maintain the electric connection between the common electrode layer and the rework pixel electrode pattern in the jumping passivation hole area even after the pixel electrode rework process, to thereby reduce the occurrence of failure and the reduction of throughput due to the rework process.

公开(公告)号：US20180138206A1

公开(公告)日：2018-05-17

申请号：US15805175

申请日：2017-11-07

Applicant: Mitsubishi Electric Corporation

Inventor： Takaharu KONOMI ,  Kazunori INOUE

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13629 ,  G02F2201/123 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: It is an object to provide a technique capable of suppressing a damage on a semiconductor channel layer due to a process of forming a source electrode and a drain electrode and also suppressing a short channel effect. A thin film transistor includes a gate electrode, a first insulating film, a source electrode, a drain electrode, a second insulating film, and a semiconductor channel layer that includes an oxide semiconductor. The second insulating film is disposed on the first insulating film, the source electrode, and the drain electrode. The semiconductor channel layer is electrically connected to the source electrode and the drain electrode via a first contact hole and a second contact hole provided in the second insulating film.

公开(公告)号：US09971220B2

公开(公告)日：2018-05-15

申请号：US14405888

申请日：2014-10-17

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Yuan Xiong

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/66

CPC classification number: G02F1/1368 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2001/136222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/66765

Abstract: A COA (Color filter On Array) substrate and a manufacturing method using the same are disclosed. The method includes: forming a first metal layer, a gate insulation layer, a color resist layer, an active layer, a second metal layer, a passivation layer, a via hole, and a transparent conductive layer in order. The via hole is used for connecting to the transparent conductive layer with the second metal layer. The transparent conductive layer is formed on the passivation layer. A gate electrode is formed by pattering the first metal layer. A drain electrode and a source electrode are formed by pattering the second metal layer. In the present invention, the color resist layer is made before the second metal layer.

公开(公告)号：US20180120610A1

公开(公告)日：2018-05-03

申请号：US15858467

申请日：2017-12-29

Applicant: Panasonic Liquid Crystal Display Co., Ltd.

Inventor： Kikuo ONO

IPC: G02F1/1343 ,  G02F1/1362

CPC classification number: G02F1/1343 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286

Abstract: A liquid crystal display device having one of the substrates including: gate signal lines extending in a row direction; data signal lines extending in a column direction; pixel electrodes and thin-film transistors, which are disposed according to pixels arrayed in the row direction and the column direction; a first insulating film formed between the pixel electrodes and the thin-film transistors; and a common electrode disposed opposite to the pixel electrodes on a liquid crystal layer side. The pixel electrodes are directly formed on a transparent substrate constituting the one of the substrates. In each of the pixels, the pixel electrode is electrically connected to a conduction electrode of the thin-film transistor through a first contact hole formed in the first insulating film, and the conduction electrode and the pixel electrode overlap each other in a plan view in a region where the first contact hole is formed.

公开(公告)号：US09958747B2

公开(公告)日：2018-05-01

申请号：US15505376

申请日：2016-08-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.

Inventor： Jinchao Bai ,  Huibin Guo ,  Yao Liu ,  Xiangqian Ding

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: G02F1/136227 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136236 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/77 ,  H01L27/12

Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are disclosed. The method for manufacturing an array substrate includes: forming a first via hole for connecting a second transparent electrically conductive layer and a gate line layer, a second via hole for connecting a first transparent electrically conductive layer and the second transparent electrically conductive layer, and a third via hole for connecting the second transparent electrically conductive layer and a source/drain electrode layer on a base substrate through patterning process; performing a filling process on the first via hole, the second via hole and the third via hole during a pattern of second transparent electrically conductive layer is being formed, such that each of the three via holes has a top surface which is flush with the second transparent electrically conductive layer surrounding the respective via holes.

公开(公告)号：US09952476B2

公开(公告)日：2018-04-24

申请号：US15127984

申请日：2015-11-17

Applicant: BOE Technology Group Co., Ltd.

Inventor： Wenbo Li ,  Pan Li

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: G02F1/13624 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/121 ,  G02F2201/123

Abstract: An array substrate and a display device are provided. The array substrate includes a plurality of data lines; a plurality of gate lines; and a plurality of sub-pixel units defined by the gate lines and the data lines intersecting each other. The sub-pixel unit includes a first pixel electrode and a second pixel electrode respectively disposed on two sides of the gate line and a common electrode disposed between the first pixel electrode and the second pixel electrode. At least a first compensation electrode is connected to at least a side of the common electrode, at least a part of projection of it on a plane having the first pixel electrode overlaps the first pixel electrode; and/or at least a second compensation electrode is connected to a side of the first pixel electrode, and at least a part of projection of it on a plane having the common electrode overlaps the common electrode. The display device can have a wide viewing angle.

公开(公告)号：US09952473B2

公开(公告)日：2018-04-24

申请号：US15581892

申请日：2017-04-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junki Jeong ,  Jisun Kim ,  Meehye Jung

IPC: H01L27/14 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  G02F1/1343 ,  H01L27/32 ,  H01L29/786

CPC classification number: G02F1/136209 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136218 ,  G02F2001/136222 ,  G02F2001/136295 ,  G02F2001/13685 ,  G02F2201/123 ,  G02F2202/10 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/7869

Abstract: A display device including: a display panel which displays an image with light, including: a substrate including: first and second light blocking areas extending in first and second directions, respectively, and a pixel area at which the image is displayed, defined by the first and second light blocking areas which intersect each other; a first shielding line and a data line spaced apart from each other on the substrate at the first light blocking area; a gate line at the second light blocking area to intersect the data line; and a thin film transistor connected to the data and gate lines. The shielding line includes a protrusion protruding toward the data line, the protrusion being overlapped by the thin film transistor. The shielding line is in a same layer of the display panel as the data line among layers disposed on the substrate of the display panel.

公开(公告)号：US20180108680A1

公开(公告)日：2018-04-19

申请号：US15837552

申请日：2017-12-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1343 ,  G09G3/36 ,  G09F21/04 ,  G02F1/167 ,  G02F1/1362 ,  G11C19/28 ,  H01L27/32

CPC classification number: H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.