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263 条记录 (耗时 0.016 秒)

    MOSFET with a thin gate insulating film
    91.
    发明申请
    MOSFET with a thin gate insulating film 失效
    具有薄栅绝缘膜的MOSFET

    公开(公告)号：US20050224898A1

    公开(公告)日：2005-10-13

    申请号：US11143594

    申请日：2005-06-03

    申请人： Hisayo Momose ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

    发明人： Hisayo Momose ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/66575 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/28211 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/78

    摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed an the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 μm; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined a be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

    摘要翻译： 半导体器件包括：p型半导体衬底（1）; 绝缘膜（3）; 经由所述绝缘膜形成所述基板的栅电极（2） 以及形成在形成在基板（1）上的栅电极（2）下方的沟道形成区域（4）的两侧的n型源极/漏极区域（5）。 特别地，在氧化硅膜的转换率（氧化硅当量厚度）下，确定绝缘膜（3）的厚度（T×OX ）小于2.5nm。 栅极（2）的栅极长度（L SUB）确定为等于或小于0.3μm; 并且进一步施加到栅电极（2）和漏区（6）的电压为1.5V以下。 因此，在具有隧穿栅极氧化膜（3）的MOSFET中，可以提高热载流子应力下的晶体管的可靠性，并且可以显着降低栅极漏电流，从而可以显着提高晶体管特性。

    Sram cell
    93.
    发明申请
    Sram cell 有权
    沙姆细胞

    公开(公告)号：US20050003612A1

    公开(公告)日：2005-01-06

    申请号：US10733612

    申请日：2003-12-11

    申请人： Douglas Hackler ,  Stephen Parke ,  Kelly Degregorio

    发明人： Douglas Hackler ,  Stephen Parke ,  Kelly Degregorio

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H03K19/0948

    CPC分类号： H01L21/2256 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66772 ,  H01L29/7832 ,  H01L29/78648 ,  H03K19/0948 ,  Y10S257/903

    摘要： A SRAM cell includes double-gated PMOS and NMOS transistors to form a latch and retain a value. The unique MOSFET transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate, and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain, and further resist compression of the channel by the source and drain.

    摘要翻译： SRAM单元包括双门控PMOS和NMOS晶体管，以形成锁存器并保持一个值。 独特的MOSFET晶体管架构提供了一个用于独立门控制的四端子器件，一个浮体器件和一个动态阈值器件。 通道可以具有U形横截面积以增加通道长度和门控制。 第一和第二绝缘间隔物设置在顶部栅极的相对侧上，使得第一间隔物在源极和顶部栅极之间，并且第二间隔物位于漏极和顶部栅极之间。 源极和漏极包括靠近间隔物延伸并连接到沟道的延伸部分。 间隔件将通道与源极和漏极的场效应隔离，并进一步抵抗通过源极和漏极的通道的压缩。

    Method for doping one side of a semiconductor body
    95.
    发明授权
    Method for doping one side of a semiconductor body 失效
    掺杂半导体本体一侧的方法

    公开(公告)号：US06448105B1

    公开(公告)日：2002-09-10

    申请号：US09647046

    申请日：2000-11-22

    申请人： Steffen Sterk

    发明人： Steffen Sterk

    IPC分类号： H01L2100

    CPC分类号： H01L31/1804 ,  H01L21/2256 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/923

    摘要： A method for doping one side of a semiconductor substrate, such as in a silicon wafer, wherein an oxide layer is deposited on both the side to be doped and the non-doped side of the semiconductor substrate. A doping layer, containing a doping agent, is deposited onto the oxide layer on the side to be doped. The doping agent passes through the oxide layer on the side to be doped and into the semiconductor substrate. The oxide layer on the non-doped side serves as a protective layer, preventing diffusion of the doping agent into the undoped side of the substrate.

    摘要翻译： 一种用于掺杂半导体衬底的一侧的方法，例如在硅晶片中，其中氧化物层沉积在半导体衬底的待掺杂侧和非掺杂侧。 含有掺杂剂的掺杂层沉积在待掺杂侧的氧化物层上。 掺杂剂通过待掺杂侧的氧化物层进入半导体衬底。 非掺杂侧的氧化物层用作保护层，防止掺杂剂扩散到衬底的未掺杂侧。

    Method to form elevated source/drain with solid phase diffused source/drain extension for MOSFET
    97.
    发明授权
    Method to form elevated source/drain with solid phase diffused source/drain extension for MOSFET 失效
    用于形成用于MOSFET的固相扩散源极/漏极扩展的源极/漏极的方法

    公开(公告)号：US5946580A

    公开(公告)日：1999-08-31

    申请号：US13429

    申请日：1998-01-26

    申请人： Shye-Lin Wu

    发明人： Shye-Lin Wu

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/417

    CPC分类号： H01L29/6659 ,  H01L21/2254 ,  H01L21/2256 ,  H01L21/2257 ,  H01L29/41783 ,  H01L29/41775 ,  H01L29/66545

    摘要： A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, a portion of the first silicon layer, and a portion of the anti-reflection layer. A shield layer is then formed over the semiconductor substrate, on the gate insulator layer, and on the first silicon layer. A spacer structure containing first conductivity type dopants is then formed on the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second conductivity type dopants is formed over the semiconductor substrate and the first silicon layer. Finally, a thermal process is performed to the semiconductor substrate for diffusing the first conductivity type dopants and the second conductivity type dopants into the semiconductor substrate.

    摘要翻译： 在半导体衬底上形成栅极绝缘体层，然后在栅极绝缘体层上形成第一硅层。 在第一硅层上形成防反射层。 通过去除栅极绝缘体层的一部分，第一硅层的一部分和抗反射层的一部分来限定栅极区。 然后在半导体衬底上，栅极绝缘体层和第一硅层上形成屏蔽层。 然后在栅极区域上形成包含第一导电类型掺杂剂的间隔结构。 在去除抗反射层之后，在半导体衬底和第一硅层之上形成含有第二导电类型掺杂剂的第二硅层。 最后，对半导体衬底进行热处理，将第一导电型掺杂剂和第二导电型掺杂剂扩散到半导体衬底中。

    Boron penetration to suppress short channel effect in P-channel device
    98.
    发明授权
    Boron penetration to suppress short channel effect in P-channel device 失效
    硼渗透抑制P沟道器件中的短沟道效应

    公开(公告)号：US5661059A

    公开(公告)日：1997-08-26

    申请号：US423109

    申请日：1995-04-18

    申请人： David Liu ,  Hao Fang

    发明人： David Liu ,  Hao Fang

    IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L21/265

    CPC分类号： H01L29/6659 ,  H01L21/2256 ,  H01L21/28061 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/4933

    摘要： A method for forming a set of p-channel devices with enhanced n-doping and penetration of boron into the channel region between the source and drain regions, thereby creating channel length independent p-channel threshold voltage behavior. Long channel and short channel transistors have approximately equal threshold voltages as (a) short channel effect is reduced with increased n-doping in short channel transistors (where boron penetration has little effect), and (b) the effects of boron penetration and increased n-doping are offset in longer channel transistors.

    摘要翻译： 一种用于形成具有增强的n掺杂和硼渗透到源极和漏极区域之间的沟道区域中的p沟道器件的集合的方法，从而产生与沟道长度无关的p沟道阈值电压特性。 长通道和短沟道晶体管具有近似相等的阈值电压，如（a）短沟道效应随着短沟道晶体管（其中硼渗透几乎没有影响）的n掺杂增加而减小，（b）硼渗透和增加的n 掺杂在较长的沟道晶体管中偏移。

    Method for making bipolar transistors using rapid thermal annealing
    100.
    发明授权
    Method for making bipolar transistors using rapid thermal annealing 失效
    使用快速热退火制造双极晶体管的方法

    公开(公告)号：US4755487A

    公开(公告)日：1988-07-05

    申请号：US904547

    申请日：1986-09-08

    申请人： Peter D. Scovell ,  Roger L. Baker ,  David W. McNeil

    发明人： Peter D. Scovell ,  Roger L. Baker ,  David W. McNeil

    IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/331 ,  H01L21/324

    CPC分类号： H01L21/2256 ,  Y10S148/09

    摘要： In making bipolar transistors, an interfacial oxide layer (5) is formed over ther monocrystalline region (1), and polysilicon (6) is formed both thereon as an extrinsic emitter region. After doping the polysilicon a monocrystalline emitter region (4) is produced in the base region by diffusion from the extrinsic polysilicon emitter region. The oxide layer (5) acts as a diffusion barrier to ensure that excessive dopant does not reach the monocrystalline region.After the above operation, a thermal treatment is effected at a higher temperature, e.g. 1100.degree. C., for a few seconds, which breaks down the interfacial oxide layer referred to above. This temporary use of the interfacial oxide layer leads to better and more consistant transistor characteristics.

    摘要翻译： 在制造双极晶体管时，在其上的单晶区域（1）上形成界面氧化物层（5），并且在其上形成多晶硅（6）作为外部发射极区域。 在掺杂多晶硅之后，通过从非本征多晶硅发射极区域的扩散在基极区域中产生单晶发射极区域（4）。 氧化物层（5）用作扩散阻挡层，以确保过量的掺杂剂不会到达单晶区域。 在上述操作之后，在更高的温度下进行热处理，例如， 1100℃，几秒钟，这破坏了上述界面氧化物层。 这种临时使用界面氧化物层导致更好和更一致的晶体管特性。