公开(公告)号：US20050101098A1

公开(公告)日：2005-05-12

申请号：US10605972

申请日：2003-11-11

申请人： Jing-Horng Gau

发明人： Jing-Horng Gau

IPC分类号： H01L21/20 ,  H01L21/322 ,  H01L21/329 ,  H01L27/06 ,  H01L27/08 ,  H01L29/93

CPC分类号： H01L29/66174 ,  H01L27/0629 ,  H01L27/0808 ,  H01L29/93

摘要： A method of forming a varactor includes forming an ion well of a first conductivity type on a substrate and a plurality of isolation structures on the ion well. The isolation structures define at least an active area on the ion well. Following that, ions of the first conductivity type are implanted into the ion well to form a doping region within the active area. A doping layer of a second conductivity type is then formed on the substrate to cover portions of the doping region. A salicide layer is formed on the doping region and the doping layer.

摘要翻译： 形成变容二极管的方法包括在衬底上形成第一导电类型的离子阱和在离子阱上形成多个隔离结构。 隔离结构至少限定了离子阱上的有效面积。 之后，将第一导电类型的离子注入到离子阱中，以在有源区内形成掺杂区。 然后在衬底上形成第二导电类型的掺杂层以覆盖掺杂区域的部分。 在掺杂区域和掺杂层上形成自对准硅化物层。

公开(公告)号：US06867107B2

公开(公告)日：2005-03-15

申请号：US10456531

申请日：2003-06-09

申请人： Akira Asai ,  Teruhito Ohnishi

发明人： Akira Asai ,  Teruhito Ohnishi

IPC分类号： H01L21/329 ,  H01L21/84 ,  H01L27/12 ,  H01L29/93 ,  H01L21/20

CPC分类号： H01L29/66174 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/93

摘要： A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n− region 132 formed in the shape of a ring and containing an n-type dopant; an anode 133 adjoined to the outer periphery of the n− region 132, the anode 133 being formed in the shape of a ring and containing a p-type dopant; and a cathode 131 adjoined to the inner periphery of the n− region 132, the third region containing an n-type dopant, wherein the dopant concentration in the n− region 132 is lower than that in each of the anode 133 and the cathode 131.

摘要翻译： 一种可变静电电容器件，包括：通过掩埋氧化膜形成在衬底上的半导体层：形成为环形并包含n型掺杂剂的n区132; 邻接于n-区132的外周的阳极133，阳极133形成为环状并含有p型掺杂剂; 以及与n区132的内周相邻的阴极131，所述第三区包含n型掺杂剂，其中所述n区132中的掺杂剂浓度低于阳极133和阴极131中的掺杂浓度 。

公开(公告)号：US20040198013A1

公开(公告)日：2004-10-07

申请号：US10829694

申请日：2004-04-22

发明人： Ted Johansson

IPC分类号： H01L021/331 ,  H01L021/8222 ,  H01L027/082

CPC分类号： H01L29/66174 ,  H01L27/0658 ,  H01L29/94

摘要： A method in the fabrication of an integrated circuit including a PMOS varactor and an npn transistor, comprises the steps of (i) simultaneously forming buried nnull-doped regions (31) for the PMOS varactor and the npn transistor in a p-doped substrate (10, 41); (ii) simultaneously forming n-doped wells (41) above the buried nnull-doped regions (31); (iii) simultaneously forming field isolation areas (81) around the n-doped regions (41); (iv) forming a PMOS gate region (111, 194) and a p-doped base each in a respective one of the n-doped wells (41); and (v) simultaneously forming nnull-doped contacts to the buried nnull-doped regions (31); the contacts being separated from the n-doped wells (41). Source and drain regions may be formed in the PMOS n-well (inversion mode) or the PMOS nnull-doped contact may be formed in the PMOS n-well instead of being separated from there (accumulation mode).

摘要翻译： 制造包括PMOS变容二极管和npn晶体管的集成电路的方法包括以下步骤：（i）同时形成用于PMOS变容二极管的n +和npn晶体管的掩埋n +掺杂区域（31） 掺杂衬底（10,41）; （ii）同时在掩埋的N +掺杂区域（31）上形成n个掺杂阱（41）; （iii）同时在n掺杂区域（41）周围形成场隔离区域（81）; （iv）在n个掺杂阱（41）中的相应一个中形成PMOS栅极区（111,194）和p掺杂的基极; 和（v）同时向掩埋的n +掺杂区域（31）形成n +掺杂的触点; 触点与n掺杂阱（41）分离。 源极和漏极区域可以形成在PMOS n阱（反转模式）中，或者可以在PMOS n阱中形成PMOS n +掺杂接触，而不是从其分离（累积模式）。

公开(公告)号：US06686640B2

公开(公告)日：2004-02-03

申请号：US10044107

申请日：2002-01-11

申请人： Bongki Mheen ,  Dongwoo Suh ,  Jin-Yeong Kang

发明人： Bongki Mheen ,  Dongwoo Suh ,  Jin-Yeong Kang

IPC分类号： H01L2993

CPC分类号： H01L29/66174 ,  H01L29/66242 ,  H01L29/93

摘要： A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

摘要翻译： 变容二极管包括第一导电类型的半导体衬底，形成在半导体衬底的上部的第二导电类型的高浓度集电区，在第一表面上形成第二导电类型的集电极区 浓度埋集电极区域，形成在高浓度埋集体区域的第二表面上的第二导电类型的高浓度集电极接触区域，形成在集电体上的第一导电类型的高浓度硅 - 锗基区域 形成在硅 - 锗基区上的金属硅化物层，形成为与金属硅化物层接触的第一电极层和形成为与集电极接触区电连接的第二电极层。

公开(公告)号：US5506442A

公开(公告)日：1996-04-09

申请号：US341141

申请日：1994-11-16

申请人： Hisashi Takemura

发明人： Hisashi Takemura

IPC分类号： H01L21/329 ,  H01L21/822 ,  H01L27/04 ,  H01L29/93 ,  H03K19/013 ,  H03K19/086 ,  H01L29/92

CPC分类号： H01L29/66174 ,  H01L29/93 ,  H03K19/0136

摘要： A variable-capacitance device has an n-type diffusion layer which has an impurity concentration profile such that a region where the impurity concentration remains substantially constant and a region where the impurity concentration changes abruptly are alternately repeated, and the impurity concentration increases as the deepness from the surface increases. The impurity concentration profile can be achieved by implanting n-type impurity atoms a plurality of times with different energies in an ion implantation process or varying the concentration of n-type impurity atoms such as of phosphorus added upon epitaxial layer growth. The variable-capacitance device, and a semiconductor integrated circuit device composed of a plurality of such variable-capacitance devices can be fabricated on a semiconductor substrate, and are highly stable.

摘要翻译： 可变电容器件具有n型扩散层，其具有杂质浓度分布，使得杂质浓度保持基本恒定的区域和杂质浓度突然变化的区域交替重复，并且杂质浓度随着深度而增加 从表面增加。 杂质浓度分布可以通过在离子注入工艺中以不同的能量注入n型杂质原子，或者改变n型杂质原子（例如在外延层生长时添加的磷）的浓度来实现。 可以在半导体衬底上制造由多个这种可变电容器件构成的可变电容器件和半导体集成电路器件，并且是高度稳定的。

公开(公告)号：US20240097002A1

公开(公告)日：2024-03-21

申请号：US17933121

申请日：2022-09-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ya-Chin LIN

IPC分类号： H01L29/66

CPC分类号： H01L29/66174

摘要： A method of forming a semiconductor structure includes forming a dielectric stack over a substrate, in which forming the dielectric stack includes forming a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer in sequence. A first hard mask layer is formed over the dielectric stack. A second hard mask layer is formed over the first hard mask layer. A patterned mask is formed over the second hard mask layer. The first and second hard mask layers are etched using the patterned mask as an etch mask to form first and second hard masks, in which the first hard mask layer is etched faster than the second hard mask layer. An opening is formed in the dielectric stack to expose the substrate. A bottom electrode layer is formed in the opening of the dielectric stack.

公开(公告)号：US20240038696A1

公开(公告)日：2024-02-01

申请号：US18225393

申请日：2023-07-24

申请人： Infineon Technologies AG

发明人： Hermann Gruber ,  Marcus Nübling ,  Jörg Busch ,  Gerrit Utz

IPC分类号： H01L23/00 ,  H01F27/32 ,  H01L29/66 ,  H01L21/768 ,  H01F27/29

CPC分类号： H01L24/02 ,  H01F27/32 ,  H01L29/66174 ,  H01L21/76829 ,  H01F27/292 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/051

摘要： An apparatus is provided that includes a substrate. In addition, the apparatus includes a first electrically conductive path arranged in a second layer above the substrate and forming a first connection of the apparatus, and a second electrically conductive pad arranged in the second layer and forming a second connection of the apparatus. An electrically conductive element is arranged in a first layer spaced apart from the second layer. The electrically conductive element forms a first capacitor with either the first pad or the second pad. In addition, a first coil is arranged in the first layer, the second layer, or in both layers. A first end of the first coil is connected to the second pad.

公开(公告)号：US20180358351A1

公开(公告)日：2018-12-13

申请号：US15621772

申请日：2017-06-13

申请人： United Microelectronics Corp.

发明人： Sheng-Huei Dai ,  Tzung-Lin Li

IPC分类号： H01L27/02 ,  H01L29/66

CPC分类号： H01L27/0255 ,  H01L27/0288 ,  H01L29/66136 ,  H01L29/66174 ,  H01L29/94

摘要： A protection device as provided includes a doped well with a first-type impurity, formed in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.

公开(公告)号：US20180315864A1

公开(公告)日：2018-11-01

申请号：US15583289

申请日：2017-05-01

申请人： QUALCOMM Incorporated

发明人： Xia LI ,  Fabio Alessio MARINO ,  Qingqing LIANG ,  Francesco CAROBOLANTE ,  Seung Hyuk KANG

IPC分类号： H01L29/93 ,  H01L29/66

CPC分类号： H01L29/93 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66174 ,  H01L29/94

摘要： Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor, and techniques for fabricating the same, implemented using a threshold voltage implant region. For example, the semiconductor variable capacitor generally includes a first non-insulative region disposed above a first semiconductor region, a second non-insulative region disposed above the first semiconductor region, and a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region. In certain aspects, the semiconductor variable capacitor also includes a control region disposed above the first semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

公开(公告)号：US20180198000A1

公开(公告)日：2018-07-12

申请号：US15913344

申请日：2018-03-06

申请人： GLOBALFOUNDRIES Inc.

发明人： Alexandru Romanescu ,  Christian Schippel ,  Nicolas Sassiat

IPC分类号： H01L29/93 ,  H01L29/66 ,  H01L27/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49

CPC分类号： H01L29/93 ,  H01L27/0629 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6659

摘要： A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.