Abstract:
A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency.
Abstract:
A solar cell includes a substrate, a selective emitter region which is positioned at the substrate and includes a lightly doped region and a heavily doped region, a first dielectric layer which is positioned on the selective emitter region and includes a plurality of first openings, which are separated from one another, and a plurality of second openings positioned around the plurality of first openings, a first electrode connected to the selective emitter region through the plurality of first openings and the plurality of second openings, and a second electrode which is positioned on the substrate and is connected to the substrate. The plurality of first openings and the plurality of second openings each have a different plane shape. The plane shape of the first opening has a line shape, and the plane shape of the second opening has a dot shape.
Abstract:
A method of fabricating single-crystalline metal silicide nanowires for anti-reflective electrodes for photovoltaics is provided that includes exposing a surface of a metal foil to oxygen or hydrogen at an elevated temperature, and growing metal silicide nanowires on the metal foil surface by flowing a silane gas mixture over the metal foil surface at the elevated temperature, where spontaneous growth of the metal silicide nanowires occur on the metal foil surface, where the metal silicide nanowires are post treated for use as an electrode in a photovoltaic cell or used directly as the electrode in the photovoltaic cell.
Abstract:
A photoelectric conversion element includes: a photoelectric conversion layer; and first and second electrodes formed on surfaces of the photoelectric conversion layer, wherein at least one of the first and second electrodes includes a translucent conductive base layer made of a translucent conductive material, and a translucent conductive mesh layer selectively buried in the translucent conductive base layer, having electrical resistivity lower than electrical resistivity of the translucent conductive base layer, and formed in a translucent conductive film pattern.
Abstract:
Discussed is a solar cell includes a semiconductor substrate, a conductive type region including a first conductive type region and a second conductive type region formed on one surface of the semiconductor substrate, an electrode including a first electrode and a second electrode, wherein the first electrode is connected to the first conductive type region and the second electrode is connected to the second conductive type region, and a passivation layer formed on the conductive type region. The passivation layer includes at least one of silicon nitride and silicon carbide.
Abstract:
The present invention relates to a solar cell. The solar cell includes a substrate of a first conductive type, the substrate having a textured surface on which a plurality of projected portions are formed, and surfaces of the projected portions having at least one of a plurality of particles attached thereto and a plurality of depressions formed thereon; an emitter layer of a second conductive type opposite the first conductive type, the emitter layer being positioned in the substrate so that the emitter layer has the textured surface; an anti-reflection layer positioned on the emitter layer which has the textured surface and including at least one layer; a plurality of first electrodes electrically connected to the emitter layer; and at least one second electrode electrically connected to the substrate.
Abstract:
A solar cell includes a photoelectric conversion layer and a front electrode on the photoelectric conversion layer. The front electrode includes a bus bar electrode; at least one first finger electrode directly connected to the bus bar electrode; a plurality of connecting electrodes extending from the bus bar electrode and having a width smaller than a width of the bus bar electrode, wherein the plurality of connecting electrodes includes portions that are spaced apart from each other to form a space therebetween; at least one second finger electrode connected to at least one of the plurality of connecting electrodes; and an auxiliary electrode formed at the space between the portions of the plurality of connecting electrodes.
Abstract:
One embodiment of the present invention provides a photovoltaic module. The photovoltaic module includes an optical concentrator and a tunneling-junction solar cell. The tunneling-junction solar cell includes a base layer, a quantum-tunneling-barrier (QTB) layer situated above the base layer, an emitter layer, a front-side electrode, and a back-side electrode.
Abstract:
The present invention relates to methods, tools and systems for manufacturing a durable and portable power-conditioned personal solar system charging apparatus. Various voltage and amperage matching algorithms are manipulated to particularize the personal solar system to power and/or charge an intended portable device or a set of intended portable devices having direct current (DC) load requirements. The optimized personal solar system that is matched to an intended device allows direct coupling to the intended device without the use of an internal battery or ancillary electronic circuit boards to distract the personal solar system output, and facilitates “fast” charging modes.
Abstract:
The method for forming a monolithically isled solar cell comprises forming a first metal layer having base and emitter metallization on a passivated backside of a semiconductor substrate. An insulating support backplane is attached to a surface of the first metal layer and at least a portion of the semiconductor substrate passivated backside. Trenches are formed through the semiconductor substrate to the insulating support backplane in a trench isolation pattern partitioning the semiconductor substrate into a plurality of monolithically isled semiconductor regions. Vias are formed in the insulating support backplane to portions of the first metal layer base and emitter metallization. A second metal layer having base and emitter metallization is formed on the insulating support backplane. The second metal layer is electrically connected to portions of the first metal layer base and emitter metallization through the vias.