公开(公告)号：US08179706B2

公开(公告)日：2012-05-15

申请号：US13111247

申请日：2011-05-19

申请人： Michael M. Abraham

发明人： Michael M. Abraham

IPC分类号： G11C11/42

CPC分类号： G06F12/0246 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C2216/14

摘要： A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function.

摘要翻译： 一种用于通过对存储器单元块的下部页面中的至少一个位进行编程来标记用于执行块管理功能的多级存储器单元块的方法和装置，使得第一逻辑状态被存储在至少一个位 在下页; 对所述存储单元块的上部页面中的至少一个位进行编程，使得所述第一逻辑状态被存储在所述上部页面中的至少一个位中; 重新编程上部页面中的至少一个位，使得至少一个位从第一逻辑状态转换到第二逻辑状态; 识别下页的至少一个比特中的第一逻辑状态以及从上一页的至少一个对应比特从第一逻辑状态到第二逻辑状态的转换; 并且作为响应，标记相应的存储器单元块以执行块管理功能。

公开(公告)号：US20080310236A1

公开(公告)日：2008-12-18

申请号：US11820003

申请日：2007-06-15

申请人： R. Jacob Baker

发明人： R. Jacob Baker

IPC分类号： G11C7/08 ,  G11C11/02 ,  G11C11/24 ,  G11C11/4091 ,  G11C11/42

CPC分类号： G11C7/22 ,  G11C5/147 ,  G11C7/065 ,  G11C7/16 ,  G11C8/08 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5634 ,  G11C2211/5644 ,  H03M3/43 ,  H03M3/456

摘要： A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes an adder with first and second inputs and an output. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the adder, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the adder.

摘要翻译： 在某些实施例中，存储器件包括连接到位线的多个存储器元件和可以连接到位线的具有数字输出和模拟输入的Δ-Σ调制器。 在一些实施例中，Δ-Σ调制器包括具有第一和第二输入和输出的加法器。 第一个输入可以连接到模拟输入。 Δ-Σ调制器还可以包括连接到加法器的输出的积分器，具有连接到积分器的输出的输入和连接到数字输出的输出的模数转换器，以及数字 - 模拟转换器，其输入连接到模数转换器的输出端，输出端连接到加法器的第二输入端。

公开(公告)号：US20070263426A1

公开(公告)日：2007-11-15

申请号：US11704221

申请日：2007-02-09

申请人： Takashi Hiraga ,  Nobutaka Tanigaki ,  Noritaka Yamamoto ,  Toshiko Mizokuro ,  Ichiro Ueno ,  Norio Tanaka ,  Hiroshi Nagaeda ,  Noriyasu Shiga

发明人： Takashi Hiraga ,  Nobutaka Tanigaki ,  Noritaka Yamamoto ,  Toshiko Mizokuro ,  Ichiro Ueno ,  Norio Tanaka ,  Hiroshi Nagaeda ,  Noriyasu Shiga

IPC分类号： G11C11/42

CPC分类号： G11C13/04 ,  G02B7/028 ,  G02F1/0126 ,  G02F3/02

摘要： A flip-flop circuit of the present invention includes a first switch and a second switch which are connected in series to each other. The first switch includes: two input ports upon which light source light and signal light are incident; two output ports for outputting an optical output; and a thermal lens forming element for forming a thermal lens in a predetermined optical inputting condition. Although the second switch is composed in the same manner as that of the first switch, a relation between the wave-lengths to be utilized is inverted. When a state is changed from OFF to ON, a pulse signal is inputted for setting and one of the rays of output light of the second switch is fed-back to the first switch so as to maintain the state of ON. When the state is changed from ON to OFF, a pulse of additional signal light is inputted. Due to the foregoing, the two states of ON and OFF can be stably maintained.

摘要翻译： 本发明的触发器电路包括彼此串联连接的第一开关和第二开关。 第一开关包括：光源光和信号光入射的两个输入端口; 两个输出端口，用于输出光输出; 以及用于在预定的光学输入条件下形成热透镜的热透镜形成元件。 虽然第二开关以与第一开关相同的方式构成，但是要使用的波长之间的关系被反转。 当状态从OFF变为ON时，输入脉冲信号以进行设置，并且将第二开关的输出光的一个反馈到第一开关，以保持ON状态。 当状态从ON变为OFF时，输入附加信号光的脉冲。 由于上述原因，可以稳定地保持ON和OFF的两个状态。

公开(公告)号：US20070211510A1

公开(公告)日：2007-09-13

申请号：US11409628

申请日：2006-04-24

申请人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

发明人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

IPC分类号： G11C11/22 ,  G11C5/06 ,  G11C11/42

CPC分类号： G11C11/22 ,  H01L27/11502

摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

摘要翻译： 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

公开(公告)号：US20060056221A1

公开(公告)日：2006-03-16

申请号：US11261535

申请日：2005-10-31

申请人： Toru Koizumi ,  Masaru Fujimura ,  Katsuhito Sakurai

发明人： Toru Koizumi ,  Masaru Fujimura ,  Katsuhito Sakurai

IPC分类号： G11C13/04 ,  H04N7/18 ,  G11C11/42

CPC分类号： H04N5/378

摘要： The present invention is mainly aimed at obtaining excellent sensor output free from periodic fixed pattern noise even if the pieces of holding capacity are converted into blocks, and the specific solution unit is described below. The signal readout unit includes: a line memory; first switches each connected to a holding capacity; a first common signal line comprising eight switches connected together; and second switches for connecting the first common signal line to the second common signal line. The control unit controls opening/closing of both switches. Between the electrode of the second switch and the second common signal line, there is provided outgoing wiring. From the control unit, control wiring a1 . . . , b1 . . . is connected to the first switch. To each wiring a1 . . . , b1 . . . , a pair of a positive signal and an anti-signal in which the logical level has been reversed with respect to each other is supplied respectively. Each wiring a1 . . . , b1 . . . is arranged so as to be line-symmetric with respect to the outgoing wiring.

公开(公告)号：US06987687B2

公开(公告)日：2006-01-17

申请号：US10715524

申请日：2003-11-19

申请人： Kinya Ashikaga

发明人： Kinya Ashikaga

IPC分类号： G11C11/22 ,  G11C11/42 ,  G11C5/06 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C11/22

摘要： A ferroelectric memory of a 1T/1C type has a pair of dummy memory cells DMC2n−1 and DMC2n. Different information have been stored in the dummy memory cells. When the information is read, out from each dummy memory cell, a potential Va is developed on a bit line BL2n−1, a potential Vb is developed on an adjacent bit line BL2n. Since the bit lines BL2n−1 and BL2n have the same capacitance, a potential Vave of each bit line which was short-circuited by a short-circuit portion s2a is equal to a just intermediate value (Va+Vb)/2 of the potentials Va and Vb. The potential Vave is applied to sense amplifiers SAn−1 and SAn as a reference potential.

摘要翻译： 1T / 1C型铁电存储器具有一对虚拟存储单元DMC 2 n-1和DMC 2 n。 不同的信息已被存储在虚拟存储器单元中。 当从每个虚拟存储器单元读出信息时，在位线BL 2 n-1上形成电位Va，在相邻位线BL 2 n上形成电位Vb。 由于位线BL 2 n-1和BL 2 n具有相同的电容，所以由短路部分s 2 a短路的每个位线的电位Vave等于刚好的中间值（Va + Vb ）/ 2的电位Va和Vb。 电位Vave被应用于读出放大器SAn-1和SAn作为参考电位。

公开(公告)号：US06872969B2

公开(公告)日：2005-03-29

申请号：US10338828

申请日：2003-01-09

申请人： Michael Redecker

发明人： Michael Redecker

IPC分类号： G02F1/1335 ,  G11C11/22 ,  G11C11/42 ,  G11C13/06 ,  H01L27/108 ,  H01L27/28 ,  H01L27/32 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L35/24 ,  H01L51/00 ,  H01L51/10

CPC分类号： H01L51/0516 ,  B82Y10/00 ,  G11C11/22 ,  H01L27/283 ,  H01L27/3225 ,  H01L27/3274 ,  H01L51/0541 ,  H01L2251/5338

摘要： A non-volatile memory device and a matrix display panel using the memory device are provided. The non-volatile memory device includes a source, a drain, an active layer, a gate insulating layer, and a gate. The active layer is formed of an organic semiconductor in a contact region between the source and the drain. The gate-insulating layer is formed of a ferroelectric material on the active layer, and the gate is formed on the gate-insulating layer. Accordingly, the non-volatile memory device and the matrix display panel are very flexible, lightweight multi-programmable and can be easily manufactured.

摘要翻译： 提供了使用存储器件的非易失性存储器件和矩阵显示面板。 非易失性存储器件包括源极，漏极，有源层，栅极绝缘层和栅极。 有源层由源极和漏极之间的接触区域中的有机半导体形成。 栅极绝缘层由有源层上的铁电材料形成，栅极形成在栅极绝缘层上。 因此，非易失性存储器件和矩阵显示面板是非常灵活的，轻便的多可编程的并且可以容易地制造。

公开(公告)号：US20050063208A1

公开(公告)日：2005-03-24

申请号：US10840803

申请日：2004-05-07

申请人： Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

发明人： Jae-Hyun Park ,  Jae-Min Yu ,  Chul-Soon Kwon ,  In-gu Yoon ,  Eung-yung Ahn ,  Jung-ho Moon ,  Yong-Sun Lee ,  Sung-Yung Jeon

IPC分类号： H01L21/8247 ,  G11C11/42 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.

摘要翻译： 提供了使用间隔物氧化工艺制造分裂栅极闪存单元的方法。 在浮栅层上形成氧化阻挡层，在氧化阻挡层中形成露出浮栅的一部分的开口。 随后，通过氧化形成具有绝缘性的材料层的开口的侧壁上的间隔物，并且在开口中形成浮栅和控制栅之间的栅间氧化层图案，同时通过执行 氧化过程。

公开(公告)号：US20050007801A1

公开(公告)日：2005-01-13

申请号：US10886302

申请日：2004-07-06

申请人： Ron Barzilai ,  Reuven Elhamias

发明人： Ron Barzilai ,  Reuven Elhamias

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/12 ,  G11C11/42

CPC分类号： G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C2211/5641

摘要： A flash non-volatile memory system that normally operates its memory cells in multiple storage states is provided with the ability to operate some selected or all of its memory cell blocks in two states instead. The two states are selected to be the furthest separated of the multiple states, thereby providing an increased margin during two state operation. This allows faster programming and a longer operational life of the memory cells being operated in two states when it is more desirable to have these advantages than the increased density of data storage that multi-state operation provides. An exemplary embodiment is as a memory card where the user can choice between two state and multi-state operation.

摘要翻译： 具有通常在多个存储状态下操作其存储器单元的闪存非易失性存储器系统具有以两种状态操作其一些所选或全部存储单元块的能力。 两个状态被选择为多个状态中最远的分离状态，从而在两个状态操作期间提供增加的余量。 这允许当多状态操作提供的数据存储器的密度增加时更有希望具有这些优点时，更快的编程和较长的存储器单元的操作寿命处于两种状态。 一个示例性实施例是存储卡，其中用户可以在两个状态和多状态操作之间进行选择。

公开(公告)号：US6072712A

公开(公告)日：2000-06-06

申请号：US311974

申请日：1999-05-14

申请人： James T. Russell

发明人： James T. Russell

IPC分类号： G11C7/00 ,  G11C13/04 ,  G11C11/42

CPC分类号： G11C13/04 ,  G11C7/005

摘要： A compact optical memory is disclosed in which data are stored in an optical data layer capable of selectively altering light such as by changeable transmissivity, reflectivity, polarization, and/or phase. The data are illuminated by controllable light sources and an array of multi-surface diffractive imaging lenslets which cause a data image to be projected onto an array of light sensors by reflecting, hence folding the image rays, by means of a Mangin mirror that both reflects and optically modifies the light rays to redirect them onto the sensor array located substantially coplanar with the data layer. Data are organized into an annular array of patches (called pages). By selective illumination of each data page, one of the lenslets images the selected data page onto a central image plane where the sensor array is located. Light in the data image pattern strikes different ones of the arrayed light sensors, thereby outputting a pattern of binary bits in the form of electrical data signals. By selectively and sequentially illuminating different ones of the data regions (pages) on the data layer, correspondingly different data patterns are imaged by the corresponding lenslets onto the common sensor array, thereby enabling many stored data images to be retrieved by multiplexing at electro-optical speed.

摘要翻译： 公开了一种紧凑的光学存储器，其中数据存储在能够选择性地改变光的光学数据层中，例如通过可变的透射率，反射率，极化和/或相位。 数据由可控光源和多表面衍射成像小透镜的阵列照亮，这些小透镜通过反射（因此折射图像光线）而使数据图像投射到光传感器阵列上，借助于两个反射 并光学地修改光线以将它们重定向到与数据层基本上共面定位的传感器阵列上。 数据被组织成一个环形阵列（称为页面）。 通过选择性地照射每个数据页，其中一个小透镜将所选择的数据页映像到传感器阵列所在的中心图像平面上。 数据图像图案中的光照射阵列光传感器中的不同的，从而以电数据信号的形式输出二进制位的图形。 通过选择性地和顺序地照射数据层上的不同数据区域（页），相应的不同数据模式被相应的小透镜成像到公共传感器阵列上，从而使许多存储的数据图像能够通过电光复用 速度。