公开(公告)号：US20240068985A1

公开(公告)日：2024-02-29

申请号：US17821836

申请日：2022-08-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Laura J. Silverstein

IPC: G01N27/414 ,  B01L3/00 ,  G01N21/05

CPC classification number: G01N27/4145 ,  B01L3/502715 ,  G01N21/05 ,  B01L2300/047 ,  B01L2300/0636 ,  B01L2300/0645

Abstract: A structure includes a lab-on-chip (LOC) sensor and frontside port and cavity features for conveying a flowable sample (fluid or gas) to a sensing element of the sensor. The cavity is confined within middle of the line (MOL) dielectric layer(s). Alternatively, the cavity includes a lower section within MOL dielectric layer(s), an upper section within back end of the line (BEOL) dielectric layer(s) in the first metal (M1) level, a divider between the sections, and a duct linking the sections. Alternatively, the cavity includes a lower portion within MOL dielectric layer(s) and an upper portion continuous with the lower portion and within BEOL dielectric layer(s) in the M1 level. Optionally, the cavity is separated from the sensing element by an additional dielectric layer and/or at least partially lined with a dielectric liner. The port extends from the top of the BEOL dielectric layers down to the cavity.

公开(公告)号：US20240061176A1

公开(公告)日：2024-02-22

申请号：US17892584

申请日：2022-08-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122

CPC classification number: G02B6/1228

Abstract: Structures for an optical coupler and methods of forming an optical coupler. The structure comprises a first waveguide core including a first tapered section, a second waveguide core including a second tapered section overlapped with the first tapered section, and an active layer including a third tapered section overlapped with the second tapered section. The first waveguide core comprises a first passive material, the second waveguide core comprises a second passive material, and the active layer comprises an active material.

公开(公告)号：US11901304B2

公开(公告)日：2024-02-13

申请号：US17323423

申请日：2021-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sunil K. Singh ,  Vibhor Jain ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  Johnatan A. Kantarovsky ,  Yves T. Ngu

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L23/481 ,  H01L23/57 ,  H01L23/573 ,  H01L2223/5442 ,  H01L2223/54433

Abstract: The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

公开(公告)号：US20240045142A1

公开(公告)日：2024-02-08

申请号：US17880006

申请日：2022-08-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Abdelsalam Aboketaf

IPC: G02B6/126 ,  G02B6/132 ,  G02B6/12

CPC classification number: G02B6/126 ,  G02B6/132 ,  G02B6/12002 ,  G02B2006/1215

Abstract: Structures for a waveguide core and methods of forming such structures. The structure comprises a stacked waveguide core including a first waveguide core and a second waveguide core stacked with the first waveguide core, and a layer adjacent to the stacked waveguide core. The layer comprises a material having a refractive index that is variable in response to a stimulus.

公开(公告)号：US11894845B1

公开(公告)日：2024-02-06

申请号：US17898937

申请日：2022-08-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Mahbub Rashed

IPC: H03K3/00 ,  H03K3/012 ,  H03K5/01 ,  H03K3/037 ,  H03K5/00

CPC classification number: H03K3/012 ,  H03K3/037 ,  H03K5/01 ,  H03K2005/00013

Abstract: Embodiments of the disclosure provide a structure and related method to delay data signals through a data path using a lockup latch driven by the inverse of a clock signal. A structure according to the disclosure provides a launch pulse latch coupled to a capture pulse latch through a data path. The data path includes a combinational logic for processing signals within the data path. An edge of a clock signal drives the launch pulse latch and the capture pulse latch. A lockup latch is within the data path between the launch pulse latch and the capture pulse latch. An inverse of the clock signal drives the lockup latch.

公开(公告)号：US11892680B2

公开(公告)日：2024-02-06

申请号：US17853186

申请日：2022-06-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/30 ,  G02B6/122 ,  G02B6/13 ,  G02B6/12

CPC classification number: G02B6/305 ,  G02B6/1228 ,  G02B6/13 ,  G02B2006/12061 ,  G02B2006/12121

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. The structure comprises an edge coupler including a first waveguide core and a second waveguide core. The first waveguide core is positioned in a vertical direction between the second waveguide core and a substrate. The first waveguide core has a first longitudinal axis, the second waveguide core has a second longitudinal axis, and the second longitudinal axis of the second waveguide core is slanted at an angle relative to the first longitudinal axis of the first waveguide core.

公开(公告)号：US20240035898A1

公开(公告)日：2024-02-01

申请号：US17874709

申请日：2022-07-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhixing ZHAO ,  Yiching CHEN ,  Oscar D. RESTREPO

IPC: G01K7/18 ,  H01L29/66

CPC classification number: G01K7/186 ,  H01L29/66825 ,  H01L29/66795

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture. The structure includes: at least one active gate structure; and a built-in temperature sensor adjacent to and on a same device level as the at least one active gate structure, the built-in temperature sensor further includes force lines and sensing lines.

公开(公告)号：US20240030160A1

公开(公告)日：2024-01-25

申请号：US18479230

申请日：2023-10-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Frank G. Kuechenmeister ,  Richard F. Taylor, III ,  Saquib B. Halim

IPC: H01L23/00 ,  G06F30/392 ,  H01L23/66 ,  H03H1/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/564 ,  G06F30/392 ,  H01L23/66 ,  H03H1/0007 ,  H01L23/585

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

公开(公告)号：US20240027685A1

公开(公告)日：2024-01-25

申请号：US17869858

申请日：2022-07-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/125 ,  G02B6/136

CPC classification number: G02B6/125 ,  G02B6/136 ,  G02B2006/12119

Abstract: Structures for a waveguide crossing and methods of fabricating a structure for a waveguide crossing. The structure comprises a first waveguide core and a second waveguide core each including a first section, a second section, and a first waveguide bend connecting the first section to the second section. The second section terminates the first waveguide core. The second section terminates the second waveguide core. The second waveguide bend has a side surface that is spaced from a side surface of the first waveguide bend by a gap. A third waveguide core is terminated by a section having an overlapping arrangement with the second section of the first waveguide core. A fourth waveguide core is terminated by a section having an overlapping arrangement with the second section of the second waveguide core.

公开(公告)号：US11881241B2

公开(公告)日：2024-01-23

申请号：US17709525

申请日：2022-03-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chandrahasa Reddy Dinnipati ,  Ramesh Raghavan ,  Bipul C. Paul

IPC: G11C11/16 ,  G11C7/06

CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675

Abstract: A structure includes an array of nonvolatile memory cells, wordlines and bitlines connected to the nonvolatile memory cells, sense amplifiers connected to the nonvolatile memory cells, and reference cells connected to the sense amplifiers. Each of the reference cells has a transistor connected to a variable resistor, one of the wordlines, a reference bitline separate from the bitlines, and the sense amplifiers.