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    Nitride semiconductor light emitting device and method of manufacturing the same
    101.
    发明申请
    Nitride semiconductor light emitting device and method of manufacturing the same 审中-公开
    氮化物半导体发光器件及其制造方法

    公开(公告)号：US20080099776A1

    公开(公告)日：2008-05-01

    申请号：US11907564

    申请日：2007-10-15

    申请人： Jin Bock Lee ,  Ho Young Song

    发明人： Jin Bock Lee ,  Ho Young Song

    IPC分类号： H01L33/00 ,  H01L21/00

    CPC分类号： H01L33/405 ,  H01L33/32 ,  H01L33/387 ,  H01L33/44

    摘要： There are provided a nitride semiconductor light emitting device and a method of manufacturing the same, the device including: a first conductivity type nitride semiconductor layer formed on a substrate; an active layer formed on the first conductivity type nitride semiconductor layer; a second conductivity type nitride semiconductor layer formed on the active layer; a light-transmitting low refractive index layer formed on the second conductivity type nitride semiconductor layer, the light-transmitting low refractive index layer having a plurality of openings through which the second conductivity type nitride semiconductor layer is partially exposed and formed of a material having a refractive index lower than a refractive index of the second conductivity type nitride semiconductor layer; and a high conductivity ohmic contact layer formed on the light-transmitting low refractive index layer and connected to the second conductivity type nitride semiconductor layer through the openings of the light-transmitting low refractive index layer.

    摘要翻译： 提供了一种氮化物半导体发光器件及其制造方法，该器件包括：形成在衬底上的第一导电型氮化物半导体层; 形成在所述第一导电型氮化物半导体层上的有源层; 形成在有源层上的第二导电型氮化物半导体层; 形成在所述第二导电型氮化物半导体层上的透光低折射率层，所述透光低折射率层具有多个开口，所述第二导电型氮化物半导体层通过所述多个开口部分地暴露并由具有 折射率低于第二导电型氮化物半导体层的折射率; 以及形成在透光低折射率层上并通过透光低折射率层的开口连接到第二导电型氮化物半导体层的高导电欧姆接触层。

    Semiconductor device and test system thereof
    102.
    发明申请
    Semiconductor device and test system thereof 有权
    半导体器件及其测试系统

    公开(公告)号：US20070034868A1

    公开(公告)日：2007-02-15

    申请号：US11499661

    申请日：2006-08-07

    申请人： Joung-Yeal Kim ,  Ho-Young Song ,  Sung-Hoon Kim

    发明人： Joung-Yeal Kim ,  Ho-Young Song ,  Sung-Hoon Kim

    IPC分类号： H01L23/58

    CPC分类号： G01R31/3173 ,  G01R31/31727

    摘要： A semiconductor device that includes a clock buffer, which generates an internal clock signal in response to a clock signal and a complementary clock signal if the semiconductor device is operating in a first mode and generates the internal clock signal in response to the clock signal and a reference voltage if the semiconductor device is operating in a second mode.

    摘要翻译： 一种半导体器件，包括时钟缓冲器，其如果半导体器件工作在第一模式中，则响应于时钟信号和互补时钟信号产生内部时钟信号，并且响应于时钟信号产生内部时钟信号，并且 如果半导体器件在第二模式下操作，则参考电压。

    Termination circuits having pull-down and pull-up circuits and related methods
    103.
    发明授权
    Termination circuits having pull-down and pull-up circuits and related methods 失效
    具有下拉和上拉电路的终端电路及相关方法

    公开(公告)号：US07157931B2

    公开(公告)日：2007-01-02

    申请号：US10765403

    申请日：2004-01-26

    申请人： Ho-young Song

    发明人： Ho-young Song

    IPC分类号： H03K19/003

    CPC分类号： H04L25/0298

    摘要： A termination circuit for a transmission line may include an input node, a pull-down circuit, and a pull-up circuit. The input node receives an input signal over the transmission line. The pull-down circuit is coupled between the input node and a first reference voltage, and the pull-down circuit may be configured to provide an electrical path between the first reference voltage and the input node responsive to the input signal having a first voltage level. The pull-up circuit is coupled between the input node and a second reference voltage, and the pull-up circuit is configured to provide an electrical path between the second reference voltage and the input node responsive to the input signal having a second voltage level. More particularly, the first reference voltage is less than the second reference voltage, and the first voltage level is greater than the second voltage level. Related methods are also discussed.

    摘要翻译： 用于传输线的终端电路可以包括输入节点，下拉电路和上拉电路。 输入节点通过传输线接收输入信号。 下拉电路耦合在输入节点和第一参考电压之间，并且下拉电路可以被配置为响应于具有第一电压电平的输入信号而在第一参考电压和输入节点之间提供电路径 。 上拉电路耦合在输入节点和第二参考电压之间，并且上拉电路被配置为响应于具有第二电压电平的输入信号而在第二参考电压和输入节点之间提供电路径。 更具体地，第一参考电压小于第二参考电压，并且第一电压电平大于第二电压电平。 还讨论了相关方法。

    Latency control circuit and method of latency control
    104.
    发明申请
    Latency control circuit and method of latency control 有权
    延迟控制电路和延时控制方法

    公开(公告)号：US20050254337A1

    公开(公告)日：2005-11-17

    申请号：US11188708

    申请日：2005-07-26

    申请人： Sang-bo Lee ,  Ho-young Song

    发明人： Sang-bo Lee ,  Ho-young Song

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00

    CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2281

    摘要： The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

    摘要翻译： 存储器件包括存储器单元阵列和从存储单元阵列寻址的数据的输出缓冲器，并且基于等待时间信号输出数据。 延迟电路基于CAS等待时间信息选择性地将至少一个传送信号与至少一个采样信号相关联，以在相关联的采样和传送信号之间产生期望的时序关系。 延迟电路根据至少一个采样信号存储读取信息，并且基于与用于存储读取的信息的采样信号相关联的传送信号产生等待时间信号。

    Delay locked-loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably
    105.
    发明授权
    Delay locked-loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably 失效
    延迟锁定环路电路，用于降低高频运行时可变延迟单元的负载，并稳定锁定外部时钟信号

    公开(公告)号：US06950488B2

    公开(公告)日：2005-09-27

    申请号：US09945599

    申请日：2001-09-04

    申请人： Dae-hyun Chung ,  Ho-young Song

    发明人： Dae-hyun Chung ,  Ho-young Song

    IPC分类号： G11C11/4076 ,  H03H11/26 ,  H03K5/14 ,  H03L7/081 ,  H03L7/089 ,  H04L7/033

    CPC分类号： H03L7/089 ,  H03K5/133 ,  H03L7/0814

    摘要： Disclosed is a delay locked-loop circuit comprising a phase detector for detecting a phase difference between an external clock signal and an internal clock signal, a delay unit controller for generating a control signal in response to output of the phase detector, and a variable delay unit for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay unit comprising a first group of delay cells used at or above a predetermined frequency, a second group of delay cells used with the first group of delay cells at or below a predetermined frequency, switch transistors for connecting/disconnecting the first group of delay cells and the second group of delay cells to/from a first output line and a second output line of the variable delay unit, respectively, in response to the control signal, and a switch for connecting/disconnecting the first output line to/from the second output line in response to a delay use signal representing the use of one of the delay cells in the first group.

    摘要翻译： 公开了一种延迟锁定环电路，包括用于检测外部时钟信号和内部时钟信号之间的相位差的相位检测器，响应于相位检测器的输出产生控制信号的延迟单元控制器，以及可变延迟 单元，用于响应于所述控制信号延迟所述外部时钟以使所述内部时钟与所述外部时钟同步，所述可变延迟单元包括在预定频率以上或以上使用的第一组延迟单元;第二组延迟单元，其与 第一组等于或低于预定频率的延迟单元，分别用于将第一组延迟单元和第二组延迟单元分别连接到可变延迟单元的第一输出线和第二输出线的开关晶体管 响应于控制信号，以及用于响应于延迟而将第一输出线与第二输出线连接/断开的开关 e信号表示使用第一组中的延迟单元之一。

    Input termination circuits and methods for terminating inputs
    106.
    发明申请
    Input termination circuits and methods for terminating inputs 失效
    输入终端电路和端接输入的方法

    公开(公告)号：US20050046442A1

    公开(公告)日：2005-03-03

    申请号：US10849322

    申请日：2004-05-19

    申请人： Ho-Young Song

    发明人： Ho-Young Song

    IPC分类号： G11C7/10 ,  H03K19/003 ,  H04L25/02

    CPC分类号： H04L25/0278 ,  H04L25/028

    摘要： An input signal provided to an input terminal is terminated by coupling the input terminal to a ground voltage through a pull down transistor if the input signal at the input terminal is at a “high” level and coupling the input terminal to a power voltage through a pull up transistor if the input signal at the input terminal is at a “low” level. Termination circuits are provided including on die termination circuits.

    摘要翻译： 如果输入端的输入信号处于“高”电平，则通过下拉晶体管将输入端耦合到接地电压来终止提供给输入端的输入信号，并将输入端耦合到电源电压 如果输入端的输入信号为“低”电平，则上拉晶体管。 提供终端电路，包括芯片终端电路。

    On-chip termination apparatus in semiconductor integrated circuit, and method for controlling the same
    107.
    发明授权
    On-chip termination apparatus in semiconductor integrated circuit, and method for controlling the same 失效
    半导体集成电路中的片上终端装置及其控制方法

    公开(公告)号：US06809546B2

    公开(公告)日：2004-10-26

    申请号：US10287136

    申请日：2002-11-04

    申请人： Ho-Young Song ,  Seong-jin Jang

    发明人： Ho-Young Song ,  Seong-jin Jang

    IPC分类号： H03K1716

    CPC分类号： H04L25/0278 ,  H03K19/018592

    摘要： Provided are an on-chip termination apparatus in a semiconductor integrated circuit, and a method for controlling the same. The on-chip termination apparatus is installed in a semiconductor integrated circuit that has an output driver for outputting data to the outside via a pad and a data input circuit for receiving data from the outside via the pad. The on-chip termination apparatus includes an on-chip terminator including at least one terminal resistor electrically connected to the pad; and a terminator control circuit for turning on or off the on-chip terminator in response to an output enable signal that enables or disables the data output circuit, wherein the terminator control circuit turns off the on-chip terminator in the event that the data output circuit is enabled. Therefore, the on-chip termination apparatus is controlled by an output enable signal, thereby reducing timing loss, thus enabling a system to operate at high speed.

    摘要翻译： 提供一种半导体集成电路中的片上终端装置及其控制方法。 片上终端装置安装在半导体集成电路中，该半导体集成电路具有用于经由焊盘向外部输出数据的输出驱动器和用于经由焊盘从外部接收数据的数据输入电路。 片上终端装置包括片上终端器，其包括电连接到该焊盘的至少一个端子电阻器; 以及用于响应于使能或禁止数据输出电路的输出使能信号来接通或关断片上终端器的终端控制电路，其中在数据输出的情况下，终端控制电路关断片上终端器 电路启用。 因此，片上终端装置由输出使能信号控制，从而减少定时损耗，从而使得系统能够以高速运行。

    Method and system for domain based packet forwarding
    109.
    发明授权
    Method and system for domain based packet forwarding 有权
    基于域的分组转发的方法和系统

    公开(公告)号：US08885647B2

    公开(公告)日：2014-11-11

    申请号：US13586915

    申请日：2012-08-16

    申请人： Chang Gyu Lim ,  Tae Yeon Kim ,  Seung Hyun Yoon ,  Ho Young Song ,  Jong Hyun Lee

    发明人： Chang Gyu Lim ,  Tae Yeon Kim ,  Seung Hyun Yoon ,  Ho Young Song ,  Jong Hyun Lee

    IPC分类号： H04L12/26

    CPC分类号： H04L63/12

    摘要： Disclosed are an apparatus and a method for swapping headers for authenticating policy based domains and tracing paths at the time of high-reliable data plane transmission. The method includes receiving packets forwarded through predetermined paths, confirming whether the received packets are normal packets, determining whether the path identification information corresponding to the paths of the received packets is present in a header information storage unit of a domain receiving the packets, swapping the headers included in the packets to swapping headers of the header information storage unit by using the identification information if it is determined that the path identification information is present, and correcting the path tracing information. By this configuration, degradation in data plane performance due to the lengths of headers can be solved.

    摘要翻译： 公开了一种用于在高可靠性数据平面传输时交换用于认证基于策略的域和跟踪路径的报头的装置和方法。 该方法包括接收通过预定路径转发的报文，确认接收到的报文是否为普通报文，确定接收报文的路径的路径识别信息是否存在于接收报文的报文头信息存储单元中， 如果确定路径识别信息存在，则通过使用识别信息来包括在分组中的头部以交换头信息存储单元的头部，并且校正路径跟踪信息。 通过这种配置，可以解决由于报头的长度导致的数据平面性能的劣化。