公开(公告)号：US10134759B2

公开(公告)日：2018-11-20

申请号：US14182601

申请日：2014-02-18

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  James Kuss

IPC: H01L21/8238 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins. The method may further include forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer, with the first group of nanowires including the first semiconductor material and the second group of nanowires including the second semiconductor material.

公开(公告)号：US20180331106A1

公开(公告)日：2018-11-15

申请号：US16035441

申请日：2018-07-13

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US20180331020A1

公开(公告)日：2018-11-15

申请号：US15594351

申请日：2017-05-12

Applicant: STMicroelectronics, Inc.

Inventor： Aaron CADAG ,  Ian Harvey ARELLANO ,  Ela Mia CADAG

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/49513 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/315 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2221/68381 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/92247

Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.

公开(公告)号：US10128327B2

公开(公告)日：2018-11-13

申请号：US14266384

申请日：2014-04-30

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L49/02 ,  H01L27/108 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11507

Abstract: An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

公开(公告)号：US10123491B2

公开(公告)日：2018-11-13

申请号：US14985128

申请日：2015-12-30

Applicant: STMicroelectronics, Inc.

Inventor： Marco De Fazio ,  Simon Dodd

IPC: A01G31/00 ,  G05B15/02 ,  A01G25/02 ,  A01G31/02 ,  A01G9/14

Abstract: The present disclosure is directed to a greenhouse or single container for plant growth coupled to the Internet of Things and including a microfluidic die for water or nutrient distribution. The microfluidic die is controllable automatically or with instructions from a remote user, based on sensors included within a growth environment.

公开(公告)号：US10117068B2

公开(公告)日：2018-10-30

申请号：US14849823

申请日：2015-09-10

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  Aidan Cully ,  David Lawrence ,  Michael Macaluso

IPC: H04W4/06 ,  H04W74/08 ,  H04L29/06 ,  H04L12/413 ,  H04L1/18 ,  H04L12/18 ,  H04B3/54 ,  H04L12/761 ,  H04L1/00

Abstract: Multicast transmissions do not allow for individual receivers to acknowledge that data was received by each receiver in the network. This is not acceptable for isochronous systems that require specific levels of QoS for each device. A multimedia communications protocol supports using multicast transmissions (one-to-many) in multimedia isochronous systems. A transmitter establishes a Multi-ACKed Multicast protocol within which a group of receiving devices can acknowledge the multicast transmission during a multi-acknowledgment period.

公开(公告)号：US20180262720A1

公开(公告)日：2018-09-13

申请号：US15978908

申请日：2018-05-14

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  James D. Allen

IPC: H04N7/18 ,  H04N5/232

CPC classification number: H04N7/181 ,  H04N5/23203 ,  H04N5/23206

Abstract: Embodiments of the present disclosure include a system and a method of accessing a system. An embodiment is a system including an imaging system including a controller and a first camera, the controller having a communication connection configured to transmit or receive content or control signals, and a mobile device including a second camera, the mobile device having a communication interface configured to transmit or receive content or control signals with the controller, the controller being configured to compare images from the first and second cameras to allow access to the controller from the mobile device.

公开(公告)号：US10075282B2

公开(公告)日：2018-09-11

申请号：US15049296

申请日：2016-02-22

Applicant: STMicroelectronics, Inc.

Inventor： Charaf Hanna ,  Benjamin Nelson Darby ,  Zhifang J Ni ,  John Wrobbel

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  H04L12/40052

Abstract: Upstream burst transmit times are dynamically communicated to the transmit unit in grants issued over time and in any order. A critical parameter is when to trigger the operation to order the buffered data stream for transmission. If the ordering operation is triggered too soon, a later grant of an earlier burst transmit time may not be accounted for and the subsequent transmission could violate the transmission order rule. If the ordering operation is triggered too late, the decision to transmit a burst at an earlier burst transmit time may violate the margin rule. To address these concerns, a fetch offset time in advance of each granted burst transmit time is assigned. As each fetch offset time is sequentially reached, a next partial data portion of the buffered data stream is prepared for burst communication.

公开(公告)号：US10067223B2

公开(公告)日：2018-09-04

申请号：US14809384

申请日：2015-07-27

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics (Research & Development) Limited

Inventor： Darin K. Winterton ,  Sam Lee

IPC: G01C3/08 ,  G01S7/486 ,  G01S17/08 ,  G01S7/48

Abstract: An electronic device includes a ranging light source and a reflected light detector. A logic circuit causes the ranging light source to emit ranging light at a target. Reflected light from the target is detected using the reflected light detector, with the reflected light being a portion of the ranging light that reflects from the target back toward the reflected light detector. An intensity of the reflected light is determined using the reflected light detector. A distance to the target is determined based upon time elapsed between activating the ranging light source and detecting the reflected ranging light. Reflectance of the target is calculated, based upon the intensity of the reflected light and the distance to the target.

公开(公告)号：US10062714B2

公开(公告)日：2018-08-28

申请号：US15177715

申请日：2016-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Bruce Doris ,  Gauri Karve ,  Qing Liu

IPC: H01L31/072 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L27/1211 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin of silicon-germanium material is formed and covered with an epitaxially grown layer of silicon material. A dummy transistor gate is then formed to extend over a channel of the fin. Sidewall spacers are formed on each side of the dummy transistor gate and directly on top of the expitaxial silicon layer. Epitaxially grown raised source and drain regions are formed on each side of the dummy transistor gate adjacent the sidewall spacers. The dummy transistor gate and a portion of the epitaxial silicon layer (underneath said dummy transistor gate) are removed and replaced by a metal gate.