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    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
    101.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
    半导体存储器件及其控制方法

    公开(公告)号：US20100302879A1

    公开(公告)日：2010-12-02

    申请号：US12847955

    申请日：2010-07-30

    申请人： Shinya FUJIOKA ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

    发明人： Shinya FUJIOKA ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

    IPC分类号： G11C5/14

    CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

    摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。

    MEMORY SYSTEM AND CONTROL METHOD FOR MEMORY
    102.
    发明申请
    MEMORY SYSTEM AND CONTROL METHOD FOR MEMORY 有权
    用于存储器的存储器系统和控制方法

    公开(公告)号：US20090154257A1

    公开(公告)日：2009-06-18

    申请号：US12257799

    申请日：2008-10-24

    申请人： Shinya FUJIOKA ,  Yasuyuki Eguchi

    发明人： Shinya FUJIOKA ,  Yasuyuki Eguchi

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C11/4074 ,  G11C2207/2227

    摘要： The memory system comprises: a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage; a first control unit that includes a control input/output circuit, which is coupled to the memory input/output circuit and operates according to the second power supply voltage; a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal; a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal; and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit.

    摘要翻译： 所述存储器系统包括：半导体存储器，其包括根据第一电源电压工作的内部电路和存储器输入/输出电路，所述存储器输入/输出电路耦合到所述内部电路并根据第二电源电压进行操作; 第一控制单元，其包括控制输入/输出电路，其耦合到所述存储器输入/输出电路并根据所述第二电源电压进行操作; 电压产生单元，其产生第二电源电压并根据电压调节信号改变第二电源电压; 时钟发生单元，其产生时钟信号并根据时钟调整信号改变时钟信号的频率; 以及第二控制单元，其根据第一控制单元的半导体存储器的访问状态生成电压调整信号和时钟调整信号。

    Semiconductor memory device
    104.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060256642A1

    公开(公告)日：2006-11-16

    申请号：US11488024

    申请日：2006-07-18

    申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

    发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08 ,  G11C7/1018 ,  G11C7/1042 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085

    摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

    摘要翻译： 字控制电路激活对应于连续模式重叠的起始行地址和下一行地址的字线。 因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也可以顺序地访问字线的切换操作。 也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。 这可以防止数据传输速率降低。 此外，不需要形成用于通知控制器正在切换字线的事实的信号和控制电路，使得可以简化控制器的半导体存储器件和控制电路的结构。 这导致系统成本的降低。

    Semiconductor memory device
    105.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07102960B2

    公开(公告)日：2006-09-05

    申请号：US11114087

    申请日：2005-04-26

    申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

    发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08 ,  G11C7/1018 ,  G11C7/1042 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085

    摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

    摘要翻译： 字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。 因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。 可以按顺序的方式访问连接到不同字线的存储单元。 也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。 这可以防止数据传输速率降低。 此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。 这导致系统成本的降低。

    Memory device
    106.
    发明申请
    Memory device 有权
    内存设备

    公开(公告)号：US20050276134A1

    公开(公告)日：2005-12-15

    申请号：US11024734

    申请日：2004-12-30

    申请人： Kaoru Mori ,  Shinya Fujioka

    发明人： Kaoru Mori ,  Shinya Fujioka

    IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C7/00 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/02

    CPC分类号： G11C11/406 ,  G11C5/147 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/5006 ,  G11C2211/4065 ,  G11C2211/4067

    摘要： A memory device is provided which has: a memory cell to store data; a word line to select the memory cell; a bit line connectable to the selected memory cell; a precharge power supply to supply a precharge voltage to the bit line; a precharge circuit to connect or disconnect the precharge power supply to or from the bit line; and a current limiting element to control the magnitude of a current flowing between the precharge power supply and the bit line at least by two steps according to an operation status.

    摘要翻译： 提供了一种存储器件，其具有：用于存储数据的存储器单元; 一个字线选择存储单元; 可选择的存储单元的位线; 预充电电源，用于向位线提供预充电电压; 预充电电路，用于将预充电电源连接到或从所述位线断开; 以及电流限制元件，用于根据操作状态至少两步地控制在预充电电源和位线之间流动的电流的大小。

    Semiconductor integrated circuit and method for testing the same
    107.
    发明授权
    Semiconductor integrated circuit and method for testing the same 失效
    半导体集成电路及其测试方法

    公开(公告)号：US06971052B2

    公开(公告)日：2005-11-29

    申请号：US10255671

    申请日：2002-09-27

    申请人： Hiroyoshi Tsuboi ,  Shinya Fujioka

    发明人： Hiroyoshi Tsuboi ,  Shinya Fujioka

    IPC分类号： G01R31/28 ,  G01R31/3181 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/46 ,  H01L21/822 ,  H01L27/04

    CPC分类号： G11C29/46 ,  G01R31/3181

    摘要： When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times. The number of times of the test command supplied to start or terminate the second and subsequent tests can be less than that of the first test. Accordingly, the time of the second and subsequent tests can be shortened. Since the first test is started only when the test command is received n times, the test is not started accidentally due to noise or the like in normal operation. Namely, the test time can be shortened without decreasing the operation reliability of an integrated circuit. Particularly, when a plurality of tests is executed successively, great benefit can be obtained.

    摘要翻译： 当接收到n次测试命令时，开始多个测试中的任何一个。 在第一次测试开始之后，每次接收到测试命令的预定次数小于n次时，任何一个测试都被启动或终止。 提供用于开始或终止第二次和后续测试的测试命令的次数可以小于第一次测试的次数。 因此，可以缩短第二次和随后的测试的时间。 由于仅在接收到n次测试命令时开始第一次测试，因此在正常操作中由于噪音等原因而不会意外启动测试。 也就是说，可以缩短测试时间而不降低集成电路的操作可靠性。 特别地，当连续执行多个测试时，可以获得很大的益处。

    Semiconductor memory device
    108.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06909644B2

    公开(公告)日：2005-06-21

    申请号：US09791815

    申请日：2001-02-26

    申请人： Shinya Fujioka ,  Hitoshi Ikeda ,  Masato Matsumiya

    发明人： Shinya Fujioka ,  Hitoshi Ikeda ,  Masato Matsumiya

    IPC分类号： G11C11/409 ,  G11C11/00 ,  G11C11/401 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/00

    CPC分类号： G11C7/065 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/4013

    摘要： The present invention provides a semiconductor memory device of a twin-storage type having an operation control method and a circuit structure that achieve a higher process rate, a less power consumption, and a smaller chip area. This semiconductor memory device includes bit lines in pairs, a sense amplifier connected to each pair of the bit lines, a first memory cell connected to one bit line of each pair of the bit lines, a second memory cell that is connected to the other bit line of each pair of the bit lines and stores the inverted data of the data stored in the first memory cell. This semiconductor memory device is characterized by not having means to pre-charge the bit lines to a predetermined potential. The semiconductor memory device of the present invention is also characterized by including a control circuit that controls the sense amplifier to start a pull-down operation after starting a pull-up operation.

    摘要翻译： 本发明提供一种双存储型半导体存储器件，其具有实现更高处理速率，更少功耗和更小芯片面积的操作控制方法和电路结构。 该半导体存储器件包括成对的位线，连接到每对位线的读出放大器，连接到每对位线的一个位线的第一存储器单元，连接到另一个位的第二存储器单元 并且存储存储在第一存储单元中的数据的反相数据。 该半导体存储器件的特征在于没有将位线预充电到预定电位的装置。 本发明的半导体存储器件的特征还在于包括控制电路，其控制读出放大器在开始上拉操作之后开始下拉操作。

    Semiconductor memory
    109.
    发明申请
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US20050073903A1

    公开(公告)日：2005-04-07

    申请号：US10994630

    申请日：2004-11-23

    申请人： Shinya Fujioka ,  Yoshiaki Okuyama

    发明人： Shinya Fujioka ,  Yoshiaki Okuyama

    IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076

    摘要： A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.

    摘要翻译： 刷新控制电路以预定的周期生成刷新请求。 第一突发控制电路根据访问命令输出预定数量的选通信号。 通过访问命令执行突发存取操作。 数据输入/输出电路连续输入要传送到存储单元阵列的数据，或者与选通信号同步地连续输出从存储单元阵列提供的数据。 当刷新请求和访问命令彼此冲突时，仲裁器确定首先执行刷新操作或突发存取操作中的哪一个。 因此，可以顺序地执行刷新操作和突发存取操作而不重叠。 结果，可以高速地输出读取数据，并且可以高速地输入写入数据。 也就是说，可以提高数据传输速率。