公开(公告)号：US12029138B2

公开(公告)日：2024-07-02

申请号：US18201741

申请日：2023-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  H01L27/0248 ,  H10B61/22

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

公开(公告)号：US12029044B2

公开(公告)日：2024-07-02

申请号：US18127651

申请日：2023-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  G11C11/161 ,  H10B61/10 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.

公开(公告)号：US12027604B2

公开(公告)日：2024-07-02

申请号：US18215787

申请日：2023-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/66462 ,  H01L21/3081 ,  H01L29/7787 ,  H01L29/2003 ,  H01L29/205

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US12027600B2

公开(公告)日：2024-07-02

申请号：US18201769

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US20240215251A1

公开(公告)日：2024-06-27

申请号：US18602040

申请日：2024-03-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H10B43/35 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/35 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate disposed on a substrate, a dielectric layer and two charge trapping layers, wherein the dielectric layer is disposed between the substrate and the memory gate, and the two charge trapping layers are disposed at two opposite sides of the memory gate, wherein each of the charge trapping layers comprises an L-shape cross-sectional profile, and two selective gates disposed on the substrate, thereby constituting a two bit memory cell, wherein a top surface of each selective gate is higher than a top surface of the memory gate.

公开(公告)号：US20240210816A1

公开(公告)日：2024-06-27

申请号：US18165937

申请日：2023-02-08

Applicant: United Microelectronics Corp.

Inventor： Chia-Chen Sun ,  En-Chiuan Liou ,  Song-Yi Lin

IPC: G03F1/70 ,  G03F1/36 ,  G06F30/392

CPC classification number: G03F1/70 ,  G03F1/36 ,  G06F30/392

Abstract: A method includes providing a layout pattern to a computer system. The layout pattern includes a first pattern, a second pattern, and a third pattern. A central line defined by connecting a line end of the second pattern and a line end of the third pattern overlaps with a middle portion of the first pattern. An optical proximity correction (OPC) is performed on the layout pattern to form a first auxiliary pattern. The first auxiliary pattern includes a first stripe pattern and a second stripe pattern both extending from the line end of the second pattern. The second stripe pattern is closer to the first pattern than the first stripe pattern, and an extending length of the second stripe pattern is less than an extending length of the first stripe pattern. The layout pattern and the first auxiliary pattern are outputted through the computer system onto a photomask.

公开(公告)号：US12022739B2

公开(公告)日：2024-06-25

申请号：US18116277

申请日：2023-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for forming a semiconductor device includes the steps of providing a substrate having a memory region and a logic region, forming a memory stack structure on the memory region, forming a passivation layer covering a top surface and sidewalls of the memory stack structure, forming a first interlayer dielectric layer on the passivation layer, performing a post-polishing etching back process to remove a portion of the first interlayer dielectric layer and a portion of the passivation layer on the top surface of the memory stack structure, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the passivation layer, and forming an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure to contact the memory stack structure.

公开(公告)号：US20240203785A1

公开(公告)日：2024-06-20

申请号：US18179377

申请日：2023-03-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Pin Hsu ,  Shih Hung Yang ,  Chu Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5283 ,  H01L29/0649

Abstract: A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

公开(公告)号：US12016250B2

公开(公告)日：2024-06-18

申请号：US17725511

申请日：2022-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

公开(公告)号：US12010931B2

公开(公告)日：2024-06-11

申请号：US17196979

申请日：2021-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H01L45/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/841 ,  H10B63/845 ,  H10N70/021 ,  H10N70/066 ,  H10N70/8833

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.